192 lines
4.3 KiB
Plaintext
192 lines
4.3 KiB
Plaintext
SiS
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SG86c201 160pin
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3C4h index 5 (R/W):
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bit 0-7 Write 0 to lock the extended registers, 86h to unlock them.
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Returns A1h when locked, 21h when unlocked
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3C4h index 6 (R/W):
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bit 0 ??
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1 Enable bank registers if set. For 256color modes this also disables
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the pixel doubling used in mode 13h.
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2-4 DAC mode. 0: Palette, 1: 32Kcolor, 2: 64Kcolor, 4: 24bit
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5 Set for interlaced modes. In interlaced modes the CRTC Offset is for
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two lines (I.e. twice the normal).
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6 Enable hardware cursor if set ?
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7 ??
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3C4h index 7 (R/W):
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bit 0-3 Clock select 2-5. If 3C2h/3CCh bits 2-3 is 3 these bits selects the
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video clock.
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4 Clock ??
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5-7 ??
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3C4h index 8 (R/W):
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bit 0-7 ??
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3C4h index 9 (R/W):
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bit 0-7 ??
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3C4h index 0Ah (R/W):
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bit 0-3 Clock ??
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4-7 CRTC Offset bits 8-11. Bits 0-7 are in 3d4h index 13h.
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3C4h index 0Bh (R/W):
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bit 0 If set all pixels are written black (some sort of color expand ?) ??
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1-2 ??
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3 If set 3CDh is the write bank and 3CBh the read bank. If clear both
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the read and write banks are in 3CDh
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4-7 ??
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3C4h index 0Ch (R/W):
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bit 0 Locks up if set ??
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1-2 memory layout (bus width ?). 0: 1Mb, 1: 2Mb, 2: 4Mb
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3 Clock ??
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4 Displays a vertically striped screen if clear ?
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5-7 ??
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3C4h index 0Dh (R):
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3C4h index 0Eh (R):
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3C4h index 0Fh (R/W):
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bit 0-1 Video Memory. 0: 1Mb, 1: 2Mb, 2: 4Mb
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2-7 ??
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3C4h index 10h (R/W):
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bit 0-7 ??
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3C4h index 11h (R/W):
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bit 0-3 ??
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4-5 Set to 3 to enable VESA DPMS ??
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6-7 Blanks screen if set ??
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3C4h index 14h 3(R/W):
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bit 0-23 Cursor Color 0
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3C4h index 17h 3(R/W):
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bit 0-23 Cursor Color 1
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3C4h index 1Ah W(R/W):
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bit 0-10 Hardware cursor X position
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3C4h index 1Ch (R/W):
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bit 0-4 Cursor X hot-spot
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3C4h index 1Dh W(R/W):
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bit 0-10 Hardware cursor Y position. For interlaced modes this is half the
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line number
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12 Set for interlaced mode w/odd cursor start line
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Note: The hardware cursor is stored as a 64x64 2bit bitmap with 4 "pixels"
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in each byte. The cursor map is at the last 16Kbytes of video memory
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Each "pixel" defines the cursor appearance as follows:
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Cursor map Appearence:
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0 Cursor Color 0 (index 14h-16h)
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1 Cursor Color 1 (index 17h-19h)
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2 Transparent (screen data)
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3 Inverse (XOR cursor)
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Note: In interlaced modes there should be two similar cursor maps of 400h
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bytes, one just after the other
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3C4h index 1Fh (R/W):
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bit 0-4 Cursor X hot-spot
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3C4h index 20h W(R/W):
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bit 0-12 Address of linear aperture in units of 512Kbytes (I.e. A19-31)
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13-14 Set to 3 to enable linear aperture ?
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3C4h index 22h
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bit 0-3 DPMS Standby
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4-7 DPMS Suspend
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3C4h index 27h (R/W):
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bit 0-3 Display Start Address bits 16-19. Bits 0-15 are in 3d4h index Ch,Dh
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3CBh (R/W):
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bit 0-5 Read bank number in units of 64Kb (if 3C4h index Bh bit 3 set)
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3CDh (R/W):
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bit 0-5 Write bank number in units of 64Kb (if 3C4h index Bh bit 3 set)
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0-3 Write bank number in units of 64Kb (if 3C4h index Bh bit 3 clear)
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4-7 Read bank number in units of 64Kb (if 3C4h index Bh bit 3 clear)
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*** Memory mapped registers ***
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M+8284h D():
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bit 0-? Destination start address
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M+8288h W():
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M+828Ah W():
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bit 0-? Scanline width
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M+828Ch D()
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bit 0-? Width & height ??
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M+8290h D():
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bit 0-? Color ?
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24-31 ROP ?
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M+8294h D():
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bit 0-? Color ?
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24-31 ROP
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M+8298h D():
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M+829Ch D();
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M+82A0h D():
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M+82A4h D():
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M+82A8h (R):
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bit 0-? Number of free command FIFO slots ?
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M+82AAh W():
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bit 3 If set source data is from CPU
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14
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15 Engine busy if set
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PCI 00h W(R): Vendor
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bit 0-15 1039h for SiS
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PCI 02h W(R): Device
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bit 0-15 1 for 86c201
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Video Modes:
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22h 132 44 TXT
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23h 132 25 TXT
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24h 132 28 TXT
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26h 80 60 TXT
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29h 800 600 PL4
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2Ah 100 40 TXT
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2Dh 640 350 P8
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2Eh 640 480 P8
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2Fh 640 400 P8
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30h 800 600 P8
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37h 1024 768 PL4
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38h 1024 768 P8
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39h 1280 1024 PL4
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40h 320 200 P15
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41h 320 200 P16
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42h 320 200 P24
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43h 640 480 P15
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44h 640 480 P16
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45h 640 480 P24
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46h 800 600 P15
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47h 800 600 P16
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48h 800 600 P24
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49h 1024 768 P15
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4Ah 1024 768 P16
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4Bh 1024 768 P24
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4Ch 1280 1024 P15
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4Dh 1280 1024 P16
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