166 lines
6.4 KiB
Plaintext
166 lines
6.4 KiB
Plaintext
Yamaha 6388 VPDC
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The Yamaha 6388 VPDC is a LCD/Plasma VGA controller. Only supports standard
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VGA modes
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3C2h (R): Misc Output Register
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bit 2-3 Select Master Clock
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0 Use CLK0 as Master Clock (Usually 25.175 MHz)
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1 Use CLK1 as Master Clock (Usually 28.322 MHz)
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2 Use CLK2 as Master Clock (Usually external)
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3 Use CLK3 as Master Clock (Usually the panel clock)
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3d4h index 72h (R/W): Video Control
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bit 0 Display on monochrome monitor/flat panel using
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Hatching for G/H code 7 if set, Grey scale if not.
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1 Enable Grey Scale/Hatching generator
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2 Enable Tonal Gradation if set.
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3 Select one of 2 16 word by 6 bit Color Palettes.
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4 Enable 64 colors on 8 color panel if set.
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5 This bit is output at the CON pin.
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3d4h index 73h (R/W): Hatching Select
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bit 0 Use Hatching for G/H code 8 if set, Grey Scale if not.
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1 Use Hatching for G/H code 9 if set, Grey Scale if not.
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2 Use Hatching for G/H code 10 if set, Grey Scale if not.
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3 Use Hatching for G/H code 11 if set, Grey Scale if not.
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4 Use Hatching for G/H code 12 if set, Grey Scale if not.
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5 Use Hatching for G/H code 13 if set, Grey Scale if not.
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6 Use Hatching for G/H code 14 if set, Grey Scale if not.
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7 Use Hatching for G/H code 15 if set, Grey Scale if not.
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3d4h index 74h (R/W): Vertical Adjust
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bit 0-7 Number of non-used lines at the top of the screen.
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For Dual Panel Single Drive use (Number of blank lines at
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the top-1)*2.
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For other types use (number of blank lines at the top)-1.
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3d4h index 75h (R/W): Raster Scan Control
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bit 0-1 Line Repeat Cycle.
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0 5 line cycle
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1 6 line cycle
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2 7 line cycle
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3 8 line cycle
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2-4 Raster Scan Correction for Dual Panels
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Set to LRC-(NLUS-NVA) mod LRC -1.
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LRC is 3d4h index 75h bit 0-1.
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NLUS is 3d4h index 78h-79h Number of Lines on Upper Screen.
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NVA is 3d4h index 74h Number of Vertical adjustments.
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Note: The Multi Raster Scan defined in this and the next register is
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used if 3d4h index 9 bit 7 is clear.
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3d4h index 76h (R/W): Raster Scan Data
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bit 0-7 Raster Scan Data. A clear bit indicates that the next scanline
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should be repeated, whereas a set bit increments the line counter.
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The bits are rotated in a 5, 6, 7 or 8 bit cycle depending on
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3d4h index 75h bit 0-1.
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3d4h index 77h (R/W): LC Adjust
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bit 0-4 Latch Clock Adjust. Number of dots times to add to
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Start and End Blanking times, as plasma and EL
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panels require strict timings.
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3d4h index 78h (R/W): Vertical Screen Size H
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bit 0 Bit 8 of the Vertical Screen Size.
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The lower 8 bits are in 3d4h index 79h.
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3d4h index 79h (R/W): Vertical Screen Size L
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bit 0-7 Vertical Screen Size bit 0-7. Bit 8 is in 3d4h index 78h.
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For full screen panels this value is the number of lines
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on the display-1 typically 479.
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For Dual Panel Single Drive types use (number of lines in
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each panel-1)*2 typically 478.
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For Dual Panel Dual Drive types use (number of lines in
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each panel-1) typically 239.
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3d4h index 7Ah (R/W): Horizontal Screen Size
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bit 0-7 Horizontal Screen Size. For Dual Panel Dual Drive types
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this is (number of dots per line)/4 -1 typically 159.
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For other types this is (number of dots per line)/8 -1
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typically 79.
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3d4h index 7Bh (R/W): M Signal Pulse Width H
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bit 0-1 Bits 8-9 of the M Signal Control.
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Lower 8 bits are in 3d4h index 7Ch.
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3d4h index 7Ch (R/W): M Signal Pulse Width L
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bit 0-7 Bits 0-7 of the M Signal Control.
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Bits 8-9 are in 3d4h index 7Bh bits 0-1.
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This sets the cycle time for reversing the polarity of the AC
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conversion signal M which is transmitted to the LCD panel.
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This is a way of controlling the brightness of the display.
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3d4h index 7Dh (R/W): Panel Control
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bit 0-1 Selects Panel Screen type.
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0 1 Screen Panel
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1 2 Screen Single Drive type
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2 2 Screen Dual Drive type.
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2-3 Selects number of bits to transfer for each pixel.
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0 = 1 bit serial, 1 = 4 bit parallel and 2 = 8 bit parallel.
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4 If set the Shift Clock is output constantly, otherwise
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only during display intervals.
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6 If set FLM is output 2 cycles delayed from VSYNC,
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if clear they are simultaneous.
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7 If set the cursor blinks at a field cycle of 32, 16 if not.
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3d4h index 7Eh (R/W): Stand By
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bit 0 If set VPDC functions are stopped and Stand-by mode is
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entered. Operation is resumed when this bit is cleared.
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If DRAMs are used for Video RAM the content of display
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memory will be lost in Stand-by mode.
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1 If set writing of the Configuration Switches Register
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(3d4h index 7Fh) from the CPU is enabled.
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3d4h index 7Fh (R/W): Configuration Switches
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bit 0-3 Display Type
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4-5 Panel/CRT connection
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0 VGA CRT (analog) connected
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1 EGA CRT (digital) connected
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2 or 3 Flat panel connected
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6 SRAM is used if set, DRAM else
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7 Scratch
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3d4h index 80h..FFh (R/W): Color Map Registers.
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bit 0-3 Color Map for color #((index#-80h)*2)
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4-7 Color Map for color #((index#-80h)*2+1)
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Note: index 80h contains color #0 and 1, index 81h color #2 and 3 et cetera.
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Grey Scale/Hatching
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The Yamaha 6388 VPDC can support both analog, digital and
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various panel, plasma and LCD displays.
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In order to display original color information on displays
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with limited colors (monochrome, 8, 16 or 64 colors/shades)
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some conversions must be made.
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The VPDC has a Color Mapping Table (CMT) which converts
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the 8bit color signal to 4 bits.
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This 4 bit code is either used directly for output
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or sent through a Grey Scale/Hatching (G/H) converter.
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G/H Code Gradation Hatching
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0 ---- OFF ----
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1 ---- 1/3 ----
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2 ---- 2/3 ----
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3 ---- ON ----
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4 ---- 1/4 ----
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5 ---- 2/4 ----
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6 ---- 3/4 ----
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7 1/5 1,3/4
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8 2/5 2,0/4
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9 3/5 2,4/4
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10 4/5 1/3 Hatch
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11 1/6 2/3 Hatch
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12 5/6 3\1 Hatch
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13 2/7 3\2 Hatch
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14 3/7 2|3 Hatch
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15 4/7 1/2 Hatch
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ID Yamaha VGA:
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if testinx2($3d4,$7c,$7c) then YAMAHA_6388
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