45 lines
1.1 KiB
Plaintext
45 lines
1.1 KiB
Plaintext
#9 Imagine 128
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304pin chip
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REG+18h
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bit 6-7 Video memory. 0: 4Mb, 1: 8Mb, 2: 16Mb, 3: 32Mb
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10
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REG+1Ch
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bit 2
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**** The PCI Interface registers ****
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Some of these may not be implemented. The ones marked with ; are in doubt
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Byte 00h W(R): Vendor ID
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bit 0-15 105Dh for ??
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Byte 02h W(R): Device ID
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bit 0-15 2309h for the Imagine 128
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Byte 10h D(R/W): Base0 (MW0 AD)
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Bit 3 (R) Pre-fetchable. Set if memory is cacheable, clear if not.
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22-31 Memory Base. Upper 10bits of the base address.
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Byte 14h D(R/W): Base1 (MW1 AD)
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Bit 22-31 Memory Base. Upper 10bits of the base address.
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Byte 18h D(R/W): Base2 (XYW AD(A))
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Bit 22-31 Memory Base. Upper 10bits of the base address.
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Byte 1Ch D(R/W): Base3 (XYW AD(B))
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Bit 22-31 Memory Base. Upper 10bits of the base address.
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Byte 20h D(R/W): Base4 (RBASE_G)
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Bit 16-31 Memory Base. Upper 10bits of the base address.
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Byte 30h D(R/W): ROM Base
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Bit 0 ROM BIOS Decode. Set to enable BIOS access
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15-31 BIOS Base Address. Upper 14-17 bits of the BIOS location. Depending
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on the BIOS size in bits 11-14 the lowest 1/2/3 bits may be forced
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to 0.
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