197 lines
7.9 KiB
Plaintext
197 lines
7.9 KiB
Plaintext
IIT AGX series
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AGX-10 Original AGX chipset. Actually consists of the AGX-10 and -11.
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AGX-14
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AGX-15 Local Bus
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AGX-16 PCI support. More clocks
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The AGX chips are basically an XGA engine with a Trident VGA part tagged on
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On the AGX-10 and -11 the XGA registers are at 21x0h-21xFh, while the AGX-14
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, -15 and -16 always have them at 2160h-216Fh.
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The AGX chips do not implement the virtual memory feature of the XGA and the
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hardware cursor is different from the XGA cursor.
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2164h-2167h are not implemented.
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216Ah index 4,Ch,Dh,38h-3Dh,62h-65h,6Bh are not implemented
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M+11h bits 0-4 not implemented
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Map width must be a power of two.
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Monochrome Map Mask (M+7Ch bit 6-7 = 2) not supported.
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3C4h index 0Bh (R): Chip Version
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bit 0-7 Chip ID. Always 2 (like 8800CS)
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Note: Writing to index Bh selects old mode registers.
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Reading from index Bh selects new mode registers.
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Note: Writing to this register in order to force old mode registers
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should be done with two 8bit writes, not one 16bit write.
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3C4h index 0Dh (R/W): Old Mode Control 2
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bit 0-2 Emulation mode
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0=VGA, 3=EGA, 5=CGA,MDA,Hercules
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4 Enable Paging mode if set. If set the CRTC offset (3d4h index 13h)
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should be multiplied by 2, and the Display Start Address (3d4h index
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0Ch & 0Dh + 1Eh bit 5 and 3C4h Old Mode index 0Eh bit 0) is in units
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of 8 bytes rather than 4 (256 color modes only).
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5 DRAM clock enabled if set.
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3C4h index 0Dh (R/W): New Mode Control 2
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Note: The old/new Mode Control 1/2 registers are selected by
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reading and writing the Chip version register (index Bh).
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3C4h index 0Eh (R/W): Old Mode Control 1
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bit 1-2 128kb Bank number (0-3)
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3 16 bit video interface if set
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3C4h index 0Eh (R/W): New Mode Control 1
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bit 0-3 64k Bank number. When writing to this field XOR with 02h, when
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reading from this field no XOR is needed.
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4-6 Reserved
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Note: The old/new Mode Control 1/2 registers are selected by
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reading and writing the Chip version register (index Bh).
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3C4h index 0Fh (R/W): Power-up Mode 2
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bit 0-3 Switch settings
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4 Bus type
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5 If set I/O address are at 3xxh, else at 2xxh.
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6 Enable ON-Card ROM if set
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7 16 bit ROM access enabled if set
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3d4h index 1Eh (R/W): Module Testing Register
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bit 0-1 ??
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2 Vertical interlace if set. In interlaced modes the CRTC offset (3d4h
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index 13h) is the number of bytes in TWO scanlines. Note that in
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interlaced modes the line doubling caused by index 9 bits 0-4,7 is
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unlikely to work, as the (even,odd) linepair is repeated rather than
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each individual line causing stripes.
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3 If set Load fonts from Bottom, from top if clear
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4 ??
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5 CRTC starting address bit 16
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6-7 ??
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3d4h index 1Fh (R/W): Software Programming Register
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bit 0-1 Memory size 0=256k, 1=512k, 2=768k, 3=1M.
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2-3 ??
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Note: This register set by software
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3d4h index 22h (R): CPU Latch Read Back
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bit 0-7 Data Latch value for current read plane.
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3d4h index 24h (R): Attribute State Read Back
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bit 0-6 Reserved
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7 Attribute Controller State
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If set the next write to 3C0h will go to the data
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register, if clear to the index register.
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3d4h index 26h (R): Attribute Index Read Back
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bit 0-7 Attribute Index Register value
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216Ah index 6Ch (R/W): AGX Mode Register 7
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bit 0 Local Bus. Set for Local Bus, clear for ISA Bus
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1 (AGX-15,16) Memory Buffer Enabled if set. Enables I/O buffering.
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May not work on some fast local bus systems.
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2 (AGX10/11) Type 'A' or 'B'
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3 (AGX10/11) Latch Delay
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4 (AGX10/11) RAS Delay Inhibit
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5 ROM, DAC Lines Disable (Not used)
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216Ah index 6Dh (R/W): AGX Mode Register 3
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bit 0 COPBASE Select. Set to place the memory mapped registers at B1F00h,
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clear to place them at D1F00h
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1 MCS16_Pull Inhibit. Set not to pull MCS16- for BIOS accesses
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2 Source Map Power of 2 Adjust. Set to add 256 to the source width to
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get 1280. For the AGX-14 this only works for 4bit/pixel modes
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3 Destination Map Power of 2. Adjust. Set to add 256 to the
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destination width to get 1280. For the AGX-14 this only works for
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4bit/pixel modes
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4 24 Bit Enable. Set to enable 24bit engine.
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5 Screen Refresh Count. Set for 25 Engine Clocks, clear for 20.
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6 PCLK Edge Enable. Set to enable pixel data on both rising and
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falling edges of PCLK
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7 24 Bit PCLK Mode. Set for 4 PCLKs in 24bit mode, clear for 3 PCLKs
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216Ah index 6Eh W(R/W): AGX Mode Register 4/5
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bit 0-9 Sprite Base Address. The start address of the cursor definition in
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units of 800h bytes. This value is XORed with 1DFh.
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Each pixel in the cursor map is interpreted as:
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0 Cursor background color (palette index 00h)
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1 Cursor foreground color (palette index FFh)
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2 Screen data (Transparent cursor)
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3 Inverted screen data (XOR cursor)
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10 X Refresh Split enabled if set
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11 Engine Delay. Set to add a wait state for local bus access
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12-13 Clock Frequency Select.
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14 Xtech Clock Select. If set bits 12-13 and bits 4-5 of index 77h
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selects the clock, if clear the clock is selected by index 54h and
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70h and possible index 77h bits 4-5.
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15 Xtech DAC Enable. Set to enable Xtech hicolor DAC
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216Ah index 71h (R/W): AGX Mode Register 8 (AGX-16 only)
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bit 0 Source Map Adjust 288. Set to add 288 to the source width.
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1 Source Map Adjust 128. Set to add 128 to the source width.
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2 Destination Map Adjust 288. Set to add 288 to the destination width
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3 Destination Map Adjust 128. Set to add 128 to the destination width
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4 Sprite Refresh
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5 Screen Refresh
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6 VRAM Ras Extend
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7 Big Buffer Enable
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216Ah index 74h (R/W): AGX Mode Register 2 (AGX10/11 only)
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bit 0 DMA Enable
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1-3 DMA Channel
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216Ah index 75h (R/W): AGX Mode Register 6 (AGX10/11 only)
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bit 0-1 Defines the address of the special cursor register.
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0: 1F0h, 1: 1E0h, 2: 1D0h, 3: 1C0h
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216Ah index 76h (R/W): AGX Mode Register 2
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bit 0 VRAM Shift Register Frequency. Set for transfer every 256 clocks,
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clear for transfer every 128 clocks (128Kx8 VRAMs)
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1 (AGX-10/11) Bus Master Overlap. Set for no Bus Master overlap on
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refresh, clear for independent Bus Master on refresh.
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Must be clear for AGX-14 and -15
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2 (AGX-10/11) Engine Clock Divide By 2. Set to divide engine clock by
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2. Must be cleared for AGX-14 and -15.
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3 Big Dac. Set for 84pin RAMDAC, clear for 44pin RAMDAC
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4 Delay Display
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5 CClk Doubled
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216Ah index 77h (R/W): AGX Mode Register 1
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bit 0 CPU Bus Size. Set for 16bit CPU Transfer, clear for 8bit
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1 CPU Wait State. Set for 1 CPU Wait State, clear for no wait states.
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Should be cleared on the -14 and -15.
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2 Interlace Toggle. Set for interlaced modes, clear for non-interlace
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4-5 Clock Frequency Select 3.
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0: 80.000MHz, 1: 50.350MHz, 2: 44.900MHz, 3: 65.000MHz
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Index 54h bits 2-3 must be 3, index 6Fh bit 6 must be 0 and index
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70h bit 7 must be 0 for these clocks to be selected.
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6 PCLK Div 2. Divide pixel clock by 2 if set ?
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7 Ext Eng Req ?
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Note: On the AGX-10/11 this register is located in index 7Fh
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216Ah index 78h (R/W): AGX Mode Register 10
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bit 0 PCI Enable
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1 1MB Aperture Enable
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2 Bus Wait State
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4 Enable 6MB
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5-6 Bank Select
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7 16Bit Pixel
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Video Modes:
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50h T 80 30
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51h T 80 43
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52h T 80 60
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53h T 132 25
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54h G 640 480 PL4
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5Bh G 800 600 PL4
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5Ch G 640 400 P8
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5Dh G 640 480 P8
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5Eh G 800 600 P8
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5Fh G 1024 768 PL4
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64h G 1024 768 P8 XGA mode
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65h G 1024 768 P8 XGA mode
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