397 lines
15 KiB
Plaintext
397 lines
15 KiB
Plaintext
Avance Logic ALG Graphics Accelerator
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The ALG chips are VGA controllers with built in graphics coprocessor (COP).
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The ALG chips only works in AT and better systems as they uses 16 bit I/O
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addresses.
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ALG2101 160pin 2Mb, 1280x1024x256c, 800x600x64k
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ALG2201 160pin As 2101, but supports 24bit color
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ALG2228 160pin 2MB, 1280x1024x256c, 1024x768x32k/64k, 800x600x16m
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ALG2301 160pin PCI version of ALG2228
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ALG2302
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ALG2064 64bit memory bus, integrates 24bit DAC & dual clock generator and
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on-chip 32K ROM
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Support chips:
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ALG1101 16bit DAC, controlled via I/O pin
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ALG1201 15/16/24bit DAC
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ALG1301 As 1201, but with video functions
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ALG3102 Clock chip. Supplies 50.35, 56.6, 44.6, 72.2, 74.9, 65.1, 84.7,
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79.4, 25.175, 28.3, 44.6, 36.1, 57.1, 63.3, 49.9, 39.7
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3C0h index 15h (R/W): Cursor Foreground
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bit 0-7 The HW cursor foreground color
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3C0h index 16h (R/W): Cursor Background
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bit 0-7 The HW cursor background color
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Note: When updating index 15h and 16h it may be necessary to explicitly
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preserve index 11h and 12h.
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3CEh index 09h (R/W): Planar Pixel Index Register
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bit 0-2 Planar Pixel Index. Selects the pixel within the CPU Latch to be
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read at 3CEh index 0Ah.
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3CEh index 0Ah (R/W): Planar Pixel Register
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bit 0-3 Planar Pixel Data. A planar pixel can be read by:
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Reading the video memory address containing the pixel, thus
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loading the CPU latches.
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Setting index 9 to the pixel number (0-7) within the byte.
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Reading this register.
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3CEh index 0Bh (R/W): Extended Function Register 1
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bit 0-1 Video Clock Division Control. Divides the video clock by:
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(2101) 0: pass through, 1: 1.5, 2: 2, 3: 4
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(2228) 0: pass through, 1: 2, 2: 4, 3: 4
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2 DRAM Clock Select. If set the DRAM clock is selected from the video
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clocks, if clear from SCLK. Only valid if 3CEh index 0Ch bit 6 is
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set.
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3-5 ??
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6-7 DRAM Clock Division Control. Divides the DRAM clock by:
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0: pass through, 1: 1.5, 2: 2, 3: 4
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3CEh index 0Ch (R/W): Extended Function Register 2
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bit 0 Vertical Retrace Interrupt Polarity Control. If set the Vertical
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Retrace Interrupt is active low, if clear active high.
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1 16-bit Video Memory Access Enable. Set if access to video memory is
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8bit, clear if 16bit.
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2 16-bit BIOS ROM Access Enable. Set if access to the BIOS ROM is
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8bit, clear if 16bit.
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3 Building Character. If set enables patterned writes where the CPU
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data is interpreted as a pattern (Color Expansion). 8 pixels are
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written at a time. '1' bits in the pattern cause the pixel to be set
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to the foreground color (3CEh index 0Dh) and '0' bits the background
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color (3CEh index 0Eh).
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4 8Maps Enable. (Packed modes only) If set 8maps are chained together
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rather than the normal 4 (Chain4). If set the Display Start Address
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(3d4h index Ch-Dh + 20h) and the Offset (3D4h index 13h) are in
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units of 8 bytes. If clear in units of 4 bytes and the pixels are
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doubled on the screen (Mode 13h).
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5 Clock Select 2. Bits 0-1 are in 3C2h/3CCh bits 2-3
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6 SCLK Selection Enable. If set enables 3CEh index 0Bh bit 2
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7 If set turns display off ?
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3CEh index 0Dh (R/W): Foreground Color Register
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bit 0-7 Used as foreground color in Color Expansion and fill color by the
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Coprocessor. In planar modes only bits 0-3 are used.
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3CEh index 0Eh (R(W): Background Color Register
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bit 0-7 Used as foreground color in Color Expansion and by the Coprocessor.
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In planar modes only bits 0-3 are used.
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3CEh index 0Fh (R/W): Extended Function Register 3
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bit 0 Polarity Control of CPU Latch Output to Function Block. If set the
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output from the CPU Latch is inverted.
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1 Polarity Control of Function Block output to Bit Mask Block. If set
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the output from the Function Block is inverted
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2 Set to enable the Read bank.
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3 Address Mapping Control. If set 1MB of video memory can be mapped to
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any 1MB bank in the first 16MB ?
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4 ??
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5 (2201 +)
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6-7 ??
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3CEh index 10h (R/W): (2201+)
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bit 0-7 ??
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3CEh index 11h (R/W): (2201+)
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bit 0-7 ??
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3CEh index 1Fh (R/W): Character ROM Extended Address Register (2101)
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bit 0-1 ??
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2 (2101 only) Clock Select 3. Bits 0-1 are in 3C2h/3CCh bits 2-3 and
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bit 2 in 3CEh index 0Ch bit 6
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3-7 ??
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3d4h index 19h (R/W): CRTC Extended Registers 1
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bit 0 Interlace Control. Set in interlaced modes. In interlaced modes the
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CRTC offset (3d4h index 13h) is for two scan lines.
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1 High Resolution Address Support in Chain 4 Mode. If set MA14 and
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MA15 wraps around, if clear MA12 and MA13 wraps around.
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Should be set enables access to video memory above 256K.
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2 Clock Lock. If set disables writes to 3C2h bits 2,3,6,7.
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3 CRTC Timing Lock. If set disables writes to the CRTC timing
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registers.
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4 New Address Scheme. If set the CRTC uses non-wrapped addresses and
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shifts them 0-2 bits left depending on sequencer mode.
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SEt in HiColor modes, but does not controll the DAC mode.
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5 Vertical Retrace Edge Control to load line address
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6 VREB4. Bit 4 of the Vertical Retrace End Register (3d4h index 11h
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bits 0-3). Only valid if bit 7 set.
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7 VRC4EN. If set the Vertical Retrace Register (3d4h index 11h bits
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0-3) is extended with bit 6 of this register.
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Note: This register can only be written when 3d4h index 1Ah bit 4 is set
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3d4h index 1Ah (R/W): CRTC Extended Register 2
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bit 0 6845 Emulation Mode. If set forces the CRTC to 6845 mode.
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1 EGA Emulation Mode. If set emulates the IBM EGA CRTC. Causes display
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to wrap at 512K ?
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2 (2228) Enable hardware cursor if set
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4 Protect Hardware Configuration. If clear disables writes to 3d4h
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index 19h, 1Dh and 3CEh index 0Bh and 0Fh. If set enables access to
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all extended registers
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5 If set causes color shifts ?
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6-7 (R) Version Number. 1: ALG2201, 3: ALG2101, 2: ALG2228/ALG2301
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3d4h index 1Bh (R): Configuration Register 1
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bits 0-7 Reserved.
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2 Set for the ALG2228, clear for the ALG2201 & ALG2301 (this could
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also be a bus ID (set for VESA, clear for PCI) or similar ??)
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3d4h index 1Ch (R/W): Configuration Register 2
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bit 0 DRAM Configuration. 0: 4 256Kx4 (512K), 1: 8/16 256Kx4
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1 Data Buffer Configuration. If clear the data bus is buffered with a
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74LS245 (or similar), if set it is unbuffered.
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2 3C3h/46E8h Select. If set the VGA Enable Port is at 3C3h, if clear
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at 46E8h.
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3 BIOS ROM Access Enabled if set
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4 Reserved (0=MCA bus, 1=ISA bus)?
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5 ROM Type. 0: 27128 (16K) ROM, 1: 27256 (32K) ROM.
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7 -MCS16 Decoding Control. If set -MCS16 is decoded from LA17-23, if
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clear from SA16-19
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Note: The contents of this register are latched from M02D0-7 on the falling
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edge of the RESET signal.
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3d4h index 1Dh (R/W): Configuration Register 3
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0 Address Latch Enable. If set the address lines are latched
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internally on the falling edge of ALE, if clear the internal latch
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is transparent.
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1 Write-per-bit. If set forces the Sequencer to support DRAM write-
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per-bit operaton ?
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3 Clock Select Pin Putput Enable. If set VCLK1, VCLK2 and VCLK3 are
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output pins, if clear input pins.
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4 Output Enable. If set enables all output pins, if clear all output
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pins except -DATAENL, DIR, -DATAENH, RAS; CKS0, CKS1 and CKS2 are
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tristated.
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5 Slot Size Detection. Set if the slot is 16bit, clear if 8bit.
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6 External Video. If set enables the P0-7, BLANK, PCLK, HSYNC and
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VSYNC pins for video output, if clear tristates them.
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Note: The contents of this register are latched from M1D0-7 on the falling
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edge of the RESET signal.
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Note: This register can only be written when 3d4h index 1Ah bit 4 is set
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3d4h index 1Eh (R/W):
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bit 0-1 Video memory. 0=256k, 1=512k, 2=1M, 3=2Mbytes.
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6-7 Max Horizontal Frequency: 0=38kHz, 1=48kHz, 2=56kHz, 3=64kHz.
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3d4h index 1Fh (R/W):
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bit 0-1 Emulation. 0=VGA, 1=EGA, 2=CGA,3=MDA
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3d4h index 20h (R/W):
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bit 0-2 Display start address bit 16-18.
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Note: if 3CEh index Ch bit 4 is set, the display start is in units of 8 bytes,
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rather than 4 as in std vga.
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3d4h index 21h (R/W): Cursor X position
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bit 0-7 Bits 3-10 of the HW cursor X position. The lower bits are in index
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25h.
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3d4h index 23h (R/W): Cursor Y position
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bit 0-7 Bits 1-8 of the HW cursor Y position. The upper bits are in index
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25h.
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Note: in non-interlaced modes (3d4h index 19h bit 0 is 0) the Y co-ordinate
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should be multiplied by 2.
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3d4h index 25h (R/W): Cursor control
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bit 0-1 Bit 9-10 of the HW cursor Y position. The lower bits are in index
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23h
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2-4 Bits 0-2 of the HW cursor X position. The upper bits are in index
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21h
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5 If set enables the HW cursor. To preserve the stability of the
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cursor, this bit should be set with each update of this register.
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6 Bit 0 of the HW cursor Y position. (see note on interlace).
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3d4h index 27h W(R/W): Cursor Map address
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bit 0-10 The address in video memory where the HW cursor map starts.
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In planar modes this address is in units of 256 bytes,
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in packed modes in units of 1024 bytes.
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The HW cursor is a 64x64 bitmap imposed on the display.
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The cursor map is stored as a 64x64x2bit array, where each pixel is:
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0: Background color (3C0h index 16h)
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1: Foreground color (3C0h index 15h)
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2: The screen data (transparent cursor).
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3: Inverted screen data (XOR cursor)
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Note: in interlaced modes the cursor is shown double height.
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3d4h index 28h (R/W): Vertical Extended reg
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bit 7 CRTC Offset bit 8. Bits 0-7 are in 3d4h index 13h
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Note: The extensions of the CRTC registers in this register are only
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active if 3d4h index 19h bit 7 is set.
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3d4h index 2Ah (R/W): Horizontal Extended reg (2201 +)
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bit 0 Horizontal Total bit 8. Bits 0-7 are in 3d4h index 00h
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3 Horizontal Blanking ??.
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4 ??
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5 ??
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Note: The extensions of the CRTC registers in this register are only active
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if 3d4h index 19h bit 7 is set.
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3D6h (R/W): Read Address Register
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bit 0-4 64k Read bank number. If 3CEh index Fh bit 2 is set all reads use
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this bank number, if clear all accesses use 3D7h.
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3D7h (R/W): Read/Write Address Register
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bit 0-4 64k Bank number. If 3CEh index Fh bit 2 is clear all accesses use
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this bank number, if set writes use this bank and reads use 3D6h.
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8280h W(R/W): Source address low
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bit 0-15 The lower 16 bits of the pixel address of the source area.
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8282h (R/W): Source address high
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bit 0-7 The upper 8 bits of the pixel address of the source area.
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Calculated as (line no.)*(pixels per line)+(pixel no. in line).
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8284h W(R/W): Source area scanline width.
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bit 0-15 The number of pixels in a scanline at the source.
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8286h W(R/W): Destination address low.
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bit 0-15 Lower 16 bits of the pixel address of the destination area.
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8288h (R/W): Destination Address high.
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bit 0-7 The upper 8 bits of the pixel address of the destination area.
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Calculated as (line no.)*(pixels per line)+(pixel no. in line).
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828Ah W(R/W): Destination area scanline width
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bit 0-15 Number of pixels in a scanline at the destination.
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828Ch W(R/W): Width of op.
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bit 0-15 Width of the blit area in pixels.
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828Eh W(R/W): Height of op.
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bit 0-15 Number of lines in the blit area.
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8290h (R/W):
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bit 0-5 7 If moving towards higher co-ordinates, 1 if moving towards lower.
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0 (or don't care) for line draws
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6 If set drawing only happens within the rectangle defined by
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8294h-9Ah.
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X co-ordinate must be >= 8294h and <=8296h.
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Y co-ordinate must be >= 8298h and <=829Ah.
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8292h W(R/W):
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bit 0-7 always 0Dh ???
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8 (Line Draw) If set the final position is to the left of the start
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9 (Line Draw) If set the final position is above the start
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10 (Line Draw) If set (Delta X) and (Delta Y) are swapped when
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calculating the Bresenham constants in 82A2h-A6h.
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11 ??
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12 Set if moving towards lower co-ordinates, clear if not.
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8294h W(R/W): Clipping left
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bit 0-15 If 8290h bit 6 is set drawing only happens if the X-co-ordinate is
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>= this value
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8296h W(R/W): Clipping right
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bit 0-15 If 8290h bit 6 is set drawing only happens if the X-co-ordinate is
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<= this value
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8298h W(R/W): Clipping top
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bit 0-15 If 8290h bit 6 is set drawing only happens if the Y-co-ordinate is
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>= this value
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829Ah W(R/W): Clipping bottom
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bit 0-15 If 8290h bit 6 is set drawing only happens if the Y-co-ordinate is
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<= this value
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829Ch W(R/W): Start X co-ordinate
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bit 0-15 Starting X co-ordinate of the destination area.
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829Eh W(R/W): Start Y co-ordinate
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bit 0-15 Starting Y co-ordinate of the destination area
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82A0h W(R/W):
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bit 0-15 Always set to 0 ??
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82A2h W(R/W): Bresenham Constant 1
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bit 0-15 The Bresenham Constant 1 used for line drawing
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Calculated as 2*(Delta Y). If 8292h bit 10 is set 2*(Delta X) is
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used.
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82A4h W(R/W): Bresenham Constant 2
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bit 0-15 The Bresenham Constant 2 used for line drawing
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Calculated as 2*((Delta Y) - (Delta X)). If 8292h bit 10 is set
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(Delta Y) and (Delta X) are swapped in the calculation.
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82A6h W(R/W): Bresenham Error Term
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bit 0-15 The Bresenham Error Term used for line drawing.
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Calculated as 2*(Delta Y) + (Delta X). If 8292h bit 10 is set
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(Delta Y) and (Delta X) are swapped in the calculation.
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82A8h W(R/W):
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bit 0-15 (Line draw) Pattern mask. Only the set bits are drawn.
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82AAh (R/W): COP status/instruction
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bit 0-3 (R) When 0 the COP is free.
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0-7 (W) Graphics instruction:
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1: Fill rectangle
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2: Copy rectangle
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4: ?
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8: Line draw
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82B0h
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82BAh (R): Status??
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bit 7 Set if busy ?
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82BCh
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82C0h
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82C8h W(R/W):
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bit
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82CAh W(R/W):
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82CCh W(R/W):
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ID Avance Logic chip:
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old:=rdinx($3d4,$1A);
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clrinx($3d4,$1A,$10); {Disable extensions}
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if not testinx($3d4,$19) then
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begin
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setinx($3d4,$1A,$10); {Enable extensions}
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if testinx($3d4,$19) and testinx2($3d4,$1A,$3F) then
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Avance Logic AL2101 !!
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end;
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wrinx($3d4,$1A,old);
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Video modes:
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20h T 132 25 16
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21h T 132 30 16
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22h T 132 43 16
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23h T 132 60 16
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24h T 80 30 16
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25h T 80 43 16
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26h T 80 60 16
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27h G 960 720 16 PL4
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28h G 512 512 256 P8
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29h G 640 400 256 P8
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2Ah G 640 480 256 P8
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2Bh G 800 600 16 PL4
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2Ch G 800 600 256 P8
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2Dh G 768 1024 16 Pl4
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2Eh G 768 1024 256 P8
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2Fh G 1024 768 4
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30h G 1024 768 16 PL4
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31h G 1024 768 256 P8
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33h G 1024 1024 256 P8
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36h G 1280 1024 16 PL4
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37h G 1280 1024 256 P8
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40h G 320 200 64k P16
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41h G 512 512 64k P16
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42h G 640 400 64k P16
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43h G 640 480 64k P16
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44h G 800 600 64k P16
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45h G 1024 768 64k P16
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48h G 640 480 16m P24
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49h G 800 600 16m P24
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