187 lines
4.8 KiB
Plaintext
187 lines
4.8 KiB
Plaintext
Ahead V5000 version A & B.
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Allows up to four boards in one system.
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103h (R/W): Multiple Chip ID Register
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bit 0-3 Must match PowerUp register (3CEh index 1Fh bits 4-7).
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3C2h (W): Misc Output Register
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bit 5 Bit 0 of bank register. (Ahead A)
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Note: This register can be read at 3CCh.
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3CEh index 0Ch (R/W): mode
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bit 0-1 Misc control. 0=standard text mode, 1=enable
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8 simultaneous fonts 2&3 reserved.
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2 Reserved
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3 High speed sequencer enable
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4 16 bit memory access enable
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5 Enhanced mode enable. Must be set for proper bank access
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6-7 Emulation mode. 0=VGA, 1=EGA, 2=Hercules and 3=CGA
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3CEh index 0Dh (R/W): Segment (Different for Ahead A and B)
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bit 0-2 (Ahead A) Bank No. bit 1-3
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Bit 0 is in 3C2h bit 5.
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0-3 (Ahead B) Read Bank No.
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4-7 (Ahead B) Write Bank No.
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3CEh index 0Eh (R/W): Clock
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bit 0 (A) Clock select bit 2. Bits 0-1 are in 3C2h/3CCh bits 2-3
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0-1 (B) Clock Select bits 2-3. Bits 0-1 are in 3C2h/3CCh bits 2-3
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2-3 Reserved
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4 If set the CLK0 (the clock selected when 3C2h/3CCh bit 2-3 = 0) is
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divided by 2, if clear it is not divided.
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5 If set the CLK1 is divided by 2, if clear it is not divided.
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6 If set the CLK2 is divided by 2, if clear it is not divided.
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7 If set the CLK3 is divided by 2, if clear it is not divided.
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3CEh index 0Fh (R/W): Master Enable Register
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bit 0-3 Chip version number (Read Only)
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0=Ahead A, 1=Ahead B
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5 Enable extended registers if set
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3CEh index 10h (R/W): Trap
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bit 0 Enable CRTC access
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1 Enable 6845 access
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2 Enable CRTC access to cause trap
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3 Enable 3B8h, 3BFh to cause trap
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4 Enable 3D8h, 3D9h to cause trap
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5 Enable 3Cxh to cause traps
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7 Select 6845 as CRT controller
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3CEh index 11h (R/W): Trap source
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bit 0 3Dxh
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1 3B5h, 3D5h
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2 3B8h, 3D8h
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3 3D9h
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4 3BFh
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5 3Cxh
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6-7 Reserved
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3CEh index 12h (R/W): Attribute
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bit 0-5 Reserved
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6 Lock VGA internal palette
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7 Enable CGA palette when in CGA mode
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3CEh index 13h (R/W): Diagnostics
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bit 0-7 Reserved
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3CEh index 14h (R/W): Lock
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bit 0 Lock Sync polarity in 3C2h bit 6,7.
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1 Lock CRTC horizontal timing
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2 Lock CRTC vertical timing
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3 Lock CRTC index 9 !Hmm.
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4 Lock CRTC index 9
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5 Lock CRTC index 0Ah, 0Bh
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6 Lock CRTC index 13h
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7 Lock Clock select in 3C2h bit 2,3.
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3CEh index 15h (R): 3B8/3D8 Readback
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bit 0-7 Mono/CGA register 3B8h/3D8h readback value
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3CEh index 16h (R): 3BF/3D9 Readback
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bit 0-5 CGA Register 3D9h readback
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6-7 Mono register 3BFh bit 0-1 Readback.
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3CEh index 17h (R/W): Miscellaneous
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bit 0 Must be 1
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1 Must be 0
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2-7 Reserved
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3CEh index 1Ch (R/W): CRTC Control
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bit 0-1 Bit 16-17 of CRTC start address
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2-3 0=normal, 3=Interlaced, 1&2 reserved.
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5 Doubles each scanline vertically if set.
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3CEh index 1Dh (R/W): Control
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bit 0-7 Reserved
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3CEh index 1Eh (R/W): Scratch
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bit 0-7 Used by BIOS for flags
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3CEh index 1Fh (R): PowerUp
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bit 0-1 Memory type. 0=2x44256 (256k), 1=4 or 16 x44256 (512K/2M),
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2=8 or 16 x4464 (256K or 512K), 3=8x44256 (1M)
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2 0 for 24k BIOS, 1 for 32k BIOS.
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3 16 bit BIOS
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4-7 Multiple Chip ID
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0= ID 0 BIOS Enabled, 1=ID 1 BIOS Enabled
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2..15 ID 2..15 Bios Disabled.
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3d4h index 19h
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3d4h index 1Dh
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3d4h index 1Eh
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46E8h (R/W): Setup Control Register
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bit 3 0 for VGA disabled, 1 for enabled
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4 0 for Setup mode, 1 for normal mode.
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5-7 Reserved
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Bank switching:
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The Ahead A has one bank register with bit 0 in 3C2h bit 5 and
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bits 1-3 in 3CEh index 0Dh.
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The Ahead B has separate read and write banks in register 3CEh index Dh.
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Memory locations:
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$C000:$25 5 bytes 'AHEAD'
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ID Ahead chipset:
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old:=rdinx($3CE,$F);
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wrinx($3CE,$F,0);
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if not testinx2($3CE,$C,$FB) then
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begin
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wrinx($3CE,$F,$20);
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if testinx2($3CE,$C,$FB) then
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begin
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case inp($3CF) and $F of
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0:Ahead A;
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1:Ahead B;
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end;
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end;
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wrinx($3CE,$F,old);
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Modes:
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22h T 132 44 16 (8x8)
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23h T 132 25 16 (8x14)
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24h T 132 28 16 (8x)
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25h G 640 480 16 planar
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26h G 640 480 16 planar
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2Fh T 160 50 16
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32h T 80 34 16
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33h T 80 34 16
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34h T 80 66 16
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42h T 80 34 4
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43h T 80 45 4
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50h T 132 25 2
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51h T 132 28 4
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52h T 132 44 2
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60h G 640 400 256 P8
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61h G 640 480 256 P8
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62h G 800 600 256 P8
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63h G 1024 768 256 P8 (Ahead B only)
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6Ah G 800 600 16 PL4
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70h G 720 396 16 PL4
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71h G 800 600 16 PL4
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74h G 1024 768 16 PL4
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75h G 1024 768 4 PL2E
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76h G 1024 768 2 PL1
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Note: Mode 75h has even bytes in planes 0&2, and odd bytes in planes 1&3.
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