659 lines
30 KiB
Plaintext
659 lines
30 KiB
Plaintext
IBM 8514/A
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8514/A clones:
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ATI 38800-1 (MACH 8), 68800 (MACH 32)
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Chips&Tech 82c480
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Paradise WD95c00/01
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0102h (R/W): Setup Control Register
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bit 0 If set the adapter is enabled, if clear the card is
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invisible to the system.
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1-7 Reserved(0)
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02E8h W(R): Display Status Register
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bit 0 SENSE is the result of a wired-OR of 3 comparators, one
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for each of the RGB video signal.
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By programming the RAMDAC for various values
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and patterns and then reading the SENSE, the monitor type
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(color, monochrome or none) can be determined.
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1 VBLANK. Vertical Blank State
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If Vertical Blank is active this bit is set.
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2 HORTOG. Horizontal Toggle
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This bit toggles every time a HSYNC pulse starts
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3-15 Reserved(0)
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02E8h W(W): Horizontal Total Register (H_TOTAL)
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bits 0-8 Horizontal Total defines the total horizontal scan line width
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including the display, blank and sync times.
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All horizontal timings are in "double nuggets"
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(8 or 10 pixels depending on the state of MEM_CNTL[0]).
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The actual value is one larger than this register.
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9-15 Reserved(0)
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Note: this register is written at 02E8 and read at 26E8h.
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02EAh (R/W): DAC Mask Register (DAC_MASK)
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bits 0-7 DAC mask. This value is anded to the pixel data before going
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to the DAC. Set to 0FFh for normal operation.
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Note: In VGA pass through mode writes to the VGA palette address 03C6h
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will go to this address to allow the 8514/A to mirror palette changes.
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02EBh (R/W): DAC Read Index Register (DAC_R_INDEX)
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bits 0-7 DAC Read Index. Indicates which of the 256 palette entries
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will be read by the current sequence of I/O read operations
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to the DAC_DATA (02EDh) register.
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Note: In VGA pass through mode writes to the VGA palette address 03C7h
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will go to this address to allow the 8514/A to mirror palette changes.
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02ECh (R/W): DAC Write Index Register (DAC_W_INDEX)
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bits 0-7 DAC Write Index. Indicates which of the 256 palette entries
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will be written by the current sequence of I/O write operations
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to the DAC_DATA (02EDh) register.
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Note: In VGA pass through mode writes to the VGA palette address 03C8h
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will go to this address to allow the 8514/A to mirror palette changes.
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02EDh (R/W): DAC DATA Register (DAC_DATA)
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bits 0-7 DAC Data.
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Note: In VGA pass through mode writes to the VGA palette address 03C9h
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will go to this address to allow the 8514/A to mirror palette changes.
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06E8h W(W): Horizontal Displayed Register (H_DISP)
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bits 0-7 Number of "double nuggets"-1 displayed in a scan line.
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8-15 Reserved(0)
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Note: In the 8514/A this register is Writeonly,
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In the Chips&Tech 82c480 it is Read/Write.
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0AE8h W(W): Horizontal Sync Start Register (H_Sync_STRT)
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bits 0-7 Hsync starts at (H_SYNC_STRT +1) double nugget periods.
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8-15 Reserved(0)
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Note: In the 8514/A this register is Writeonly,
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In the Chips&Tech 82c480 it is Read/Write.
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0EE8h W(W): Horizontal Sync Width Register (H_SYNC_WID)
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bits 0-4 Width of the Horizontal Sync pulse in "double nuggets".
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5 Horizontal Sync Polarity (HSYNCPOL).
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If set the Horizontal Sync Pulse is Negative, else Positive.
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6-15 Reserved(0)
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Note: In the 8514/A this register is Writeonly,
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In the Chips&Tech 82c480 it is Read/Write.
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12E8h W(W): Vertical Total Register (V_TOTAL)
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bits 0-2 Vertical Total Adjust (VTADJ).
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3-11 Vertical Total Base (VTB).
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The Vertical Total is calculated as:
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Vertical Total = (Scan Modulos * VTB)+VTADJ+1
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Where the Scan Modulos is found from the DBLSCAN and
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MEMCFG bits of the DISP_CNTL register (22E8h).
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DBLSCAN: MEMCFG: Scan Modulos:
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0 0 0 2
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0 0 1 4
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0 1 0 6
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0 1 1 8
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1 0 0 4
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1 0 1 8
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1 1 0 12
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1 1 1 16
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12-15 Reserved(0)
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Note: In the 8514/A this register is Writeonly,
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In the Chips&Tech 82c480 it is Read/Write.
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16E8h W(W): Vertical Displayed Register (V_DISP)
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bits 0-2 Vertical Displayed Adjust (VDADJ)
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3-11 Vertical Displayed Base (VDB)
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The Vertical Displayed is calculated as:
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Vertical Displayed = (Scan Modulos * VDB)+VDADJ+1
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Where the Scan Modulos is the same as for
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Vertical Total in 12E8h.
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12-15 Reserved(0)
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Note: In the 8514/A this register is Writeonly,
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In the Chips&Tech 82c480 it is Read/Write.
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1AE8h W(W): Vertical Sync Start Register (V_SYNC_STRT)
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bits 0-2 Vertical Sync Start Adjust (VSADJ)
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3-11 Vertical Sync Start Base (VSB)
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The Vertical Sync Start is calculated as:
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Vertical Sync Start = (Scan Modulos * VSB)+VSADJ+1
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Where the Scan Modulos is the same as for
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Vertical Total in 12E8h.
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12-15 Reserved(0)
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Note: In the 8514/A this register is Writeonly,
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In the Chips&Tech 82c480 it is Read/Write.
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1EE8h W(W): Vertical Sync Width Register (V_SYNC_WID)
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bits 0-4 Number of scanlines in the Vertical Sync pulse.
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5 Vertical Sync Polarity (VSYNCPOL).
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If set the Vertical Sync pulse is Negative, else Positive.
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6-15 Reserved(0)
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Note: In the 8514/A this register is Writeonly,
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In the Chips&Tech 82c480 it is Read/Write.
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22E8h W(W): Display Control Register (DISP_CNTL)
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bit 0 Odd Bank Enable (ODDBNKENAB).
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If set use Horizontally Interleaved banks.
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(Normal 8514/A mode).
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1-2 Memory Configuration (MEMCFG).
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0 NCLK (PS8 Mode)
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1 NCLK/2 (Normal 8514/A Mode)
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2 NCLK/3
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3 NCLK/4
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3 (Double Scan) DBLSCAN. If set doublescan is enabled.
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4 INTERLACE. Interlace if set.
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5-6 Display Enable (DISPEN)
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0 = No effect
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1 = Enable Hsync, Vsync, Blank, data transfer cycles
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and refresh cycles.
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2,3 = Disable Hsync, Vsync, Blank, data transfer cycles
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and refresh cycles.
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7-15 Reserved(0)
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Note: In the 8514/A this register is Writeonly,
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In the Chips&Tech 82c480 it is Read/Write.
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26E8h W(R): Horizontal Total Register (H_TOTAL)
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Note: this register is written at 02E8 and read at 26E8h.
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2EE8h W(R): Subsystem Control Register (SUBSYS_CNTL)
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Note: In the original IBM 8514/A this register is Write only.
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In the CT82c480 it is written to 42E8h and read from 2EE8h.
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42E8h W(R): Subsystem Status Register (SUBSYS_STAT)
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bit 0-3 Interrupt requests. These bits show the state of internal interrupt
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requests. An interrupt will only occur if the corresponding bit(s)
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in SUBSYS_CNTL is set. Interrupts can only be reset by writing a 1
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to the corresponding Interrupt Clear bit in SUBSYS_CNTL.
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Bit 0: VBLNKFLG
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1: PICKFLAG
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2: INVALIDIO
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3: GPIDLE
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4-6 MONITORID.
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1: IBM 8507 (1024x768) Monochrome
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2: IBM 8514 (1024x768) Color
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5: IBM 8503 (640x480) Monochrome
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6: IBM 8512/13 (640x480) Color
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7 8PLANE.
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(CT82c480) This bit is latched on reset from pin P4D7.
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8-11 CHIP_REV. Chip revision number.
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12-15 (CT82c480) CHIP_ID. 0=CT 82c480.
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42E8h W(W): Subsystem Control Register (SUBSYS_CNTL)
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bit 0-3 Interrupt Reset. Write 1 to a bit to reset the interrupt.
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Bit 0 RVBLNKFLG Write 1 to reset Vertical Blank interrupt.
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1 RPICKFLAG Write 1 to reset PICK interrupt.
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2 RINVALIDIO Write 1 to reset Queue Overflow/Data
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Underflow interrupt.
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3 RGPIDLE Write 1 to reset GPIDLE interrupt.
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4-7 Reserved(0)
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8 IBLNKFLG. If set Vertical Blank Interrupts are enabled.
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9 IPICKFLAG. If set PICK Interrupts are enabled.
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10 IINVALIDIO. If set Queue Overflow/Data Underflow Interrupts are
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enabled.
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11 IGPIDLE. If set Graphics Engine Idle Interrupts are enabled.
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12-13 CHPTEST. Used for chip testing.
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14-15 Graphics Processor Control (GPCTRL).
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Note: In the original IBM 8514/A this register is Write only.
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In the CT82c480 it is written to 42E8h and read from 2EE8h.
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46E8h W(W): ROM Page Select Register (ROM_PAGE_SEL)
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bit 0-2 Maps a 4KB page of the onboard 32K ROM to address C7000h-C7FFFh.
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3 VGA Enable. If set enables the VGA
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This bit is not implemented in the 8514/A, but in the VGA
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controller.
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4 VGA Setup. If set the VGA is in Setup mode.
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This bit is not implemented in the 8514/A, but in the VGA
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controller.
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5-15 Reserved(0)
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Note: In the 8514/A this register is Writeonly,
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In the Chips&Tech 82c480 it is Read/Write.
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4AE8h W(W): Advanced Function Control Register (ADVFUNC_CNTL)
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bit 0 DISABPASSTHRU. If clear the VGA video is passed through the
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8514/A RAMDAC, if set the 8514/A video is passed to the 8514/A
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RAMDAC.
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1 RSDV0. Reserved bit 0 = 1.
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2 Clock Select (CLKSEL).
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If set a clock of 44.900MHz is used (1024x768 interlaced)
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if clear a clock of 25.175MHz is used (640x480).
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The CT82c480 supports 8 clock frequencies through the
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Extended Configuration Register EC3 (5EE8h).
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3 RSDV1. Reserved bit 1 =0.
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4-15 Reserved(0).
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Note: In the 8514/A this register is Writeonly,
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In the Chips&Tech 82c480 it is Read/Write.
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52E8h W(R/W): Extended Configuration Register (EC0) (CT82c480 only)
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bit 0-15 Reserved.
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56E8h W(R/W): Extended Configuration Register (EC1) (CT82c480 only)
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bit 0-15 Reserved.
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5AE8h W(R/W): Extended Configuration Register (EC2) (CT82c480 only)
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bit 0-2 Reserved(1)
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3-4 ROMBASE. Latched on reset from P4D3-4.
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Determines start address of ROM:
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8K ROM 32K ROM
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MC ISA MC ISA MC =Micro Channel
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0 0C8000 C6000 0D0000 D0000
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1 0D8000 D8000 0D8000 D8000
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2 0C0000 C0000 0C0000 C0000
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3 0C6000 C8000 0C8000 C8000
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5 ROMSIZE. Latched on reset from P4D5.
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If set the ROM is 8K, if clear the ROM is 32K.
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6 ROMPAGING. Latched from P4D6 on reset.
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If set the ROMPG pins are outputs, if clear they are inputs.
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7 8 Bit planes (8BP).
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8-9 BANKS. Number of VRAM banks.
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0=1 bank, 1=2 banks, 2=3 banks, 3=4 banks.
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10 If set 256Kx4 VRAMs are used, if clear 64Kx4 VRAMs.
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Sampled from MA8 on reset.
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11 5-Pixel Nuggets (5PN). Latched from WE4/ on reset.
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Determines whether there are 4 or 5 pixels to a nugget.
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12 Reserved(0)
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13 8-bit DAC Control (8BITDAC). If set the RAMDAC is 8bit rather than
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6bit. On reset the 8BITDAC pin is sampled, then the pin turns into
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an output driven by this bit. This can be used to switch a DAC with
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6/8bit ability like an IMSG178 or BT478 between 6 and 8 bits.
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14-15 Reserved(0)
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5EE8h W(R/W): Extended Configuration Register (EC3) (CT82c480 only)
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bit 0-3 Selects which registers will be read from BEE8h.
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4 Alternate High Register Select (AHRS). If set writes to video
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timing registers will go to the Alternate-High register set.
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5 Alternate Low Register Select (ALRS). If set writes to video timing
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registers will go to the Alternate-Low register set.
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6 Alternate High Register Enable (AHRE). If set enables the Alternate
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High-resolution video timing register set.
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7 Alternate Low Register Enable (ALRE). If set enables the Alternate
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Low-resolution video timing register set.
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8-10 Clock Select 0-2 (CLKSEL0-2). The CT82c480 maintains 3 different
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clock select register sets. On set each for Alternate High,
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Alternate Low and normal video.
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11 Reserved(0)
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12 OVERRIDE. If set the normal video register set is used.
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If clear the AHRE and ALRE determines the video register set used.
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This bit is reset on any write to the ADVFUNC_CTRL register (4AE8h)
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13-15 Reserved(0)
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Note: Writes to this register should be 8-bit.
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82E8h W(R/W): Current Y Position Register (CUR_Y)
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bit 0-11 Y Position. Y co-ordinate of current position in pixels.
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12-15 Reserved(0)
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86E8h W(R/W): Current X Position Register (CUR_X)
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bit 0-11 X Position. X co-ordinate of current position in pixels.
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12-15 Reserved(0).
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Note: In 5PN mode bits 11, 1 and 0 are remainder bits, bits 2-10 are the
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current X position modulo 5.
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8AE8h W(R/W): Destination Y Position & Axial Step Constant Register
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(DESTY_AXSTP)
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bit 0-11 During BITBLT operations this is the Y co-ordinate of the
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destination in pixels. During Line Drawing, this is the Bresenham
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constant 2*dminor. (dminor is the length of the line projected
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onto the minor or dependent axis).
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12 AXSTPSIGN. Sign bit for Axial Step Constant.
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Should be 0 during BITBLT operations.
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13-15 Reserved(0)
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Note: In the original IBM 8514/A this register is Write only. In the CT82c480
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it is read/writable
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8EE8h W(R/W): Destination X Position & Diagonal Step Constant Register
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(DESTX_DISTP)
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bit 0-11 During BITBLT operations this is the X co-ordinate of the
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destination in pixels.
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During Line Drawing this is the Bresenham constant 2*dminor-
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2*dmajor. (dminor is the length of the line projected onto
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the minor or dependent axis, dmajor is the length of the
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line projected onto the major or independent axis)
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12 DGSTPSIGN. Sign bit for Diagonal Step Constant
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(Should be set to 0 for BITBLT operations).
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13-15 Reserved(0)
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Note: In the original IBM 8514/A this register is Write only. In the CT82c480
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it is read/writable
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92E8h W(R/W): Error Term Register (ERR_TERM).
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bit 0-12 Initial Error Term. This register is programmed to the Bresenham
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initial error term before a line drawing command is issued.
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13-15 Reserved. These bits are read/writable but have no function.
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96E8h W(R/W): Major Axis Pixel Count & Rectangle Width Register
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(MAJ_AXIS_PCNT)
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bit 0-10 For BITBLT and rectangle commands this is the width of the area.
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For Line Drawing this is the Bresenham constant dmajor.
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Must be positive.
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11-15 Reserved(0)
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Note: In the original IBM 8514/A this register is Write only.
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In the CT82c480 it is read/writable
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9AE8h W(R): Graphics Processor Status Register (GP_STAT)
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bit 0-7 Queue State.
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00h = 8 words available - queue is empty
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01h = 7 words available
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03h = 6 words available
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07h = 5 words available
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0Fh = 4 words available
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1Fh = 3 words available
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3Fh = 2 words available
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7Fh = 1 word available
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FFh = 0 words available - queue is full
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8 DATARDY. If set data is ready to be read from
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the PIX_TRANS register (E2E8h).
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9 Graphics Processor Busy (GPBUSY)
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If set the Graphics Processor is busy.
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10-15 Reserved(0)
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9AE8h W(W): Command Register (CMD)
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bit 0 WRTDATA. If set VRAM write operations are enabled. If clear
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operations execute normally but no writes to memory is performed.
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1 PLANAR defines the orientation of the display bitmap.
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0=Through plane mode, 1=Across plane mode.
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2 If set the last pixel of a line command (CMD_LINE, SSV or LINEAF)
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is not drawn. This is used for mixes such as XOR where drawing the
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same pixel twice would give the wrong color.
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For rectangle commands the effect is different depending on the
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INC_X and INC_Y fields:
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CMD_RECT
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If INC_X is set then the rightmost column is not drawn,
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if clear the leftmost column is not drawn.
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CMD_RECTV1
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If INC_Y is set the bottom row is not drawn,
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if clear the top row is not drawn.
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CMD_RECTV2
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No effect
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CMD_BITBLT
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If INC_X set the rightmost column is not drawn,
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if clear the leftmost column is not drawn.
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3 LINETYPE.
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0: Bresenham line drawing
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CMD_LINE draws a line using the Bresenham algorithm as
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specified in the DESTY_AXSTP (8AE8h), DESTX_DIASTP (8EE8h),
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ERR_TERM (92E8h) and MAJ_AXIS_PCNT (96E8h) registers
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1: Vector line draws.
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CMD_NOP allows drawing of Short Stroke Vectors (SSVs) by
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writing to the Short Stroke register (9EE8h).
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CMD_LINE draws a vector of length MAJ_AXIS_PCNT (96E8h)
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in the direction specified by LINEDIR (bits 5-7).
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4 DRAW. If clear the current position is moved, but no pixels
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are modified. This bit should be set when attempting read or
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write of bitmap data.
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5-7 LINEDIR. When a line draw command (CMD_LINE) with LINETYPE=1
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is issued, these bits define the direction of the line
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counter clockwise relative to the positive X-axis.
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0 = 000 degrees
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1 = 045 degrees
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2 = 090 degrees
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3 = 135 degrees
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4 = 180 degrees
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5 = 225 degrees
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6 = 270 degrees
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7 = 315 degrees
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5 INC_X. This bit together with INC_Y determines which quadrant
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the slope of a line lies within. They also determine the
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orientation of rectangle draw commands.
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If set lines are drawn in the positive X direction (left to right).
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6 YMAJAXIS. For Bresenham line drawing commands this bit determines
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which axis is the independent or major axis. INC_X and INC_Y
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determines which quadrant the slope falls within. This bit further
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defines the slope to within an octant.
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If set Y is the major (independent) axis.
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7 INC_Y. This bit together with INC_X determines which quadrant
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the slope of a line lies within. They also determine the
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orientation of rectangle draw commands.
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If set lines are drawn in the positive Y direction (down).
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8 (Pixel Data Enable) PCDATA.
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If set the drawing engine waits for read/write of the PIX_TRANS
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register (E2E8h) for each pixel during a draw operation.
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9 16BIT. If set the PIX_TRANS register (E2E8h) is processed
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internally as two bytes in the order specified by BYTSEQ.
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If clear all accesses are 8bit.
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10-11 Reserved(0)
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12 Byte Sequence (BYTSEQ). Affects both reads and writes of
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SHORT_STROKE (9EE8h) and PIX_TRANS (E2E8h) when 16bit=1.
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If set take low byte first, if clear take high byte first.
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13-15 Draw Command:
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0 = CMD_NOP. (Should be used for Short Stroke Vectors).
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1 = CMD_LINE
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2 = CMD_RECT (Fill rectangle in X direction)
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3 = CMD_RECTV1 (Fill rectangle in Y direction)
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4 = CMD_RECTV2 (Fast filled Y direction rectangle)
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5 = CMD_LINEAF (Outline)
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6 = CMD_BITBLT (Copy rectangle)
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7 = illegal
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9EE8h W(R/W): Short Stroke Vector Transfer Register (SHORT_STROKE)
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bit 0-3 Length of vector projected onto the major axis.
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This is also the number of pixels drawn.
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4 Must be set for pixels to be written.
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5-7 VECDIR. The angle measured counter-clockwise from horizontal
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right) at which the line is drawn,
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0 = 000 degrees
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1 = 045 degrees
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2 = 090 degrees
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3 = 135 degrees
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4 = 180 degrees
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5 = 225 degrees
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6 = 270 degrees
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7 = 315 degrees
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8-15 The lower 8 bits are duplicated in the upper 8 bits so two
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short stroke vectors can be drawn with one command.
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Note: The upper byte must be written for the SSV command to be executed.
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Thus if a byte is written to 9EE8h another byte must be written to
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9EE9h before execution starts. A single 16bit write will do.
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If only one SSV is desired the other byte can be set to 0.
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Note: In the original IBM 8514/A this register is Write only.
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In the CT82c480 it is read/writable
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A2E8h W(W): Background Color Register (BKGD_COLOR)
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bit 0-7 Background Color. This is the color used for writing pixels
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where the Foreground Color Mix is selected and FSS=0, or the
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Background Color Mix is selected and BSS=0.
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8-15 Reserved(0)
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Note: During drawing commands reading this register is equivalent to
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reading the PIX_TRANS register (E2E8h).
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This register is writable when GPBUSY=DATARDY=0 or when PCDATA=0.
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Otherwise during drawing commands with PCDATA=1 a write to A2E8h
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functions as a write to the PIX_TRANS register.
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A6E8h W(W): Foreground Color Register (FRGD_COLOR)
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bit 0-7 Foreground Color. This is the color used for writing pixels
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where the Foreground Color Mix is selected and FSS=1, or the
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Background Color Mix is selected and BSS=1.
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8-15 Reserved(0)
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Note: During drawing commands reading this register is equivalent to
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reading the PIX_TRANS register (E2E8h).
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This register is writable when GPBUSY=DATARDY=0 or when PCDATA=0.
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Otherwise during drawing commands with PCDATA=1 a write to A6E8h
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functions as a write to the PIX_TRANS register.
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AAE8h W(R/W): Write Mask Register (WRT_MASK)
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bit 0-7 Writemask. A plane can only be modified if the corresponding
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bit is set.
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8-15 Reserved(0)
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Note: In the original IBM 8514/A this register is Write only.
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In the CT82c480 it is read/writable
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AEE8h W(R/W): Read Mask Register (RD_MASK)
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bit 0-7 Read Mask affects the following commands: CMD_RECT, CMD_BITBLT
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and reading data in Across Plane Mode.
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Each bit set prevents the plane from being read.
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8-15 Reserved(0)
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Note: In the original IBM 8514/A this register is Write only.
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In the CT82c480 it is read/writable
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B2E8h W(R/W): Color Compare Register (COLOR_CMP)
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bit 0-7 This is an 8 bit color which is compared to the destination
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data during BitBlts. The arithmetic comparison to be used
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(<,>,=,true,false, etc..) is specified by the COLCMPO bits
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of the PIX_CNTL register.
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If the result of the comparison is true, the destination data
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is left unchanged.
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8-15 Reserved(0)
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Note: In the original IBM 8514/A this register is Write only.
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In the CT82c480 it is read/writable
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B6E8h W(R/W): Background Mix Register (BKGD_MIX)
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bit 0-4 Background MIX (BACKMIX).
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00 not DST
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01 0 (false)
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02 1 (true)
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03 2 DST
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04 not SRC
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05 SRC xor DST
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06 not (SRC xor DST)
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07 SRC
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08 not (SRC and DST)
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09 (not SRC) or DST
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0A SRC or (not DST)
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0B SRC or DST
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0C SRC and DST
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0D SRC and (not DST)
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0E (not SRC) and DST
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0F not (SRC or DST)
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10 min(SRC,DST)
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11 DST-SRC with underflow
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12 SRC-DST with underflow
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13 SRC+DST with overflow
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14 max(SRC,DST)
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15 (DST-SRC)/2 with underflow
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16 (SRC-DST)/2 with underflow
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17 (SRC+DST)/2 with overflow
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18 DST-SRC with saturate
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19 DST-SRC with saturate
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1A SRC-DST with saturate
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1B SRC+DST with saturate
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1C (DST-SRC)/2 with saturate
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1D (DST-SRC)/2 with saturate
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1E (SRC-DST)/2 with saturate
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1F (SRC+DST)/2 with saturate
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DST is always the destination bitmap, bit SRC has four
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possible sources selected by the BSS bits.
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5-6 Background Source Select (BSS)
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0 BSS is Background Color
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1 BSS is Foreground Color
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2 BSS is Pixel Data from the PIX_TRANS register (E2E8h)
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3 BSS is Bitmap Data (Source data from display buffer).
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7-15 Reserved(0)
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Note: In the original IBM 8514/A this register is Write only.
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In the CT82c480 it is read/writable
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BAE8h W(R/W): Foreground Mix Register (FRGD_MIX)
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bit 0-4 Foreground MIX (FOREMIX).
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Same as BACKMIX in B6E8h.
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5-6 Foreground Source Select (FSS)
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0 FSS is Background Color
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1 FSS is Foreground Color
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2 FSS is Pixel Data from the PIX_TRANS register (E2E8h)
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3 FSS is Bitmap Data (Source data from display buffer).
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7-15 Reserved(0)
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Note: In the original IBM 8514/A this register is Write only.
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In the CT82c480 it is read/writable
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BEE8h W(W): Multifunction Control Register (MULTIFUNC_CTRL)
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bit 0-11 Data.
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12-15 INDEX. indicates which Multifunction register
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will be written with the data in bits 0-11.
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Note: Several registers are placed at BEE8h. When BEE8 is written
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the bits 12-15 selects the specific register to receive the write.
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Note: In the original IBM 8514/A these registers are write-only.
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The CT 82c480 allows reading the registers by writing the index
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to bits 0-3 of the Extended Configuration Register 3 (5EE8h)
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and then reading BEE8h. Bits 12-15 read are not valid.
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BEE8h index 00h W(W): Minor Axis Pixel Count Register (MIN_AXIS_PCNT).
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bit 0-10 Height of BITBLT or rectangle command.
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Actual height is one larger.
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11 Reserved(0)
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Note: See note above on reading BEE8h.
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BEE8h index 01h W(W): Top Scissors Register (SCISSORS_T).
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bit 0-11 Minimum Y co-ordinate value for the scissors rectangle.
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Note: See note above on reading BEE8h.
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BEE8h index 02h W(W): Left Scissors Registers (SCISSORS_L).
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bit 0-11 Minimum X co-ordinate value for the scissors rectangle.
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Note: See note above on reading BEE8h.
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BEE8h index 03h W(W): Bottom Scissors Register (SCISSORS_B).
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bit 0-11 Maximum Y co-ordinate value for the scissors rectangle.
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Note: See note above on reading BEE8h.
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BEE8h index 04h W(W): Right Scissors Register (SCISSORS_R).
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bit 0-11 Maximum X co-ordinate value for the scissors rectangle.
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Note: See note above on reading BEE8h.
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BEE8h index 05h W(W): Memory Control Register (MEM_CNTL).
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bit 0-1 HORCFG. Xco-ordinate divider.
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0=4, 1=5, 2=8 and 3=10.
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Bit 0 is set if using 5-pixel operations
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and bit 1 is set if the VRAMs are interleaved horizontally.
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2-3 VRTCFG. VRAM banks.
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If using 256KBit banks 0=2 banks and 1=4banks.
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If using 1MBit banks 1=1 Bank, 2=2 banks and 3=4 banks.
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4 BUFSWP. Used to select planes when in Pseudo 8-plane mode.
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If set buffer 1 (upper 4 planes) is selected.
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If clear buffer 0 (lower 4 planes) is selected.
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5-11 Reserved(0)
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Note: See note above on reading BEE8h.
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BEE8h index 08h W(W): Fixed Pattern Low Register (PATTERN_L).
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bit 0-4 Mask low is used to select the mix on a pixel by pixel basis.
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If MIXSEL=01 then test pattern registers are used to select
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ForeGround or background mix. Mask Low applies to even numbered
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nuggets (0 is leftmost on the screen).
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A 0 selects BACKMIX and a 1 selects FOREMIX.
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Bit 4 is pixel 0 and bit 0 is pixel 4 (if in 5PN mode).
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5-11 Reserved(0)
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Note: See note above on reading BEE8h.
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BEE8h index 09h W(W): Fixed Pattern High Register (PATTERN_H).
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bit 0-4 Mask low is used to select the mix on a pixel by pixel basis.
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If MIXSEL=01 then test pattern registers are used to select
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ForeGround or background mix. Mask High applies to odd numbered
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nuggets (0 is leftmost on the screen).
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A 0 selects BACKMIX and a 1 selects FOREMIX.
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Bit 4 is pixel 0 and bit 0 is pixel 4 (if in 5PN mode).
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5-11 Reserved(0)
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Note: See note above on reading BEE8h.
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BEE8h index 0Ah W(W): Pixel Control Register (PIX_CNTL).
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BIT 0 Intra-Nugget Alignment (INA5PN).
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If set BitBlt data in the internal data buffer is aligned on
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Modulos 5 basis rather than Modulos 4.
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1-2 PLANEMODE.
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0 Normal Operation
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1 Indeterminate
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2 Fill area using RD_MASK as boundary mask.
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Does not fill second edge of boundary;
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Plane Mask is a mixture of RD_MASK and WRT_MASK.
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3 Fill area using WRT_MASK as boundary mask.
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Does fill second edge of boundary;
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Plane Mask is WRT_MASK (although RD_MASK must be
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non-zero for correct operation).
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3-5 Color Comparison operation (COLCMPOP).
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Determines the comparison performed on each pixel.
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0 False (always write DST)
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1 true (never write DST)
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2 DST >= COLOR_CMP
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3 DST < COLOR_CMP
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4 DST <> COLOR_CMP
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5 DST = COLOR_CMP
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6 DST <= COLOR_CMP
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7 DST > COLOR_CMP
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6-7 Mix Select (MIXSEL).
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0 FOREMIX is always used.
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1 PATTERN_L,PATTERN_H select mix.
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2 Data from PIX_TRANS selects the mix (1=FOREMIX).
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3 SRC selects mix (used for transparency during BITBLT).
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8-11 Reserved(0)
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Note: See note above on reading BEE8h.
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E2E8h W(R/W): Pixel Data Transfer Register (PIX_TRANS)
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bit 0-15 Data can be read from or written to the display buffer.
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In through plane mode (PLANAR=0), bits 0-7 and 8-15 map onto
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bit planes 0-7 of an individual pixel.
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In across plane mode (PLANAR=1) bits 0-4 and 8-12 map onto pixels
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0-4 within a nugget (1 bit per pixel).
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Note: The original IBM 8514/A should always be accessed with 16bit read/writes
|
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Note: The original IBM 8514/A can also access this register at A2E8h and A6E8h
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during drawing commands.
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