302 lines
8.7 KiB
Plaintext
302 lines
8.7 KiB
Plaintext
ARK Logic
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ARK1000VL 160pin original version. No PCI support ?
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ARK1000PV PCI bus version of 1000VL
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ARK2000PV 208pin 64bit memory interface. 16bit path to DAC
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3C4h index 10h (R/W):
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bit 0-1 Should be set to 3 to access all of video memory
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2-3 Set to 3 to enable memory mapped engine regs at A800h, 0 to disable
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4 Set to enable the Linear frame buffer
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5 ?
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6 (1000) Video Memory Size. 0: 1MB, 1: 2MB
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6-7 (2000) Video Memory Size. 0: 1MB, 1: 2MB, 2: 4MB, 3: 8MB
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3C4h index 11h (R/W): Video Clock Select
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bit 0-1 Giant Shift Register Mode.
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0 ??
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1 If set pixels are doubled horizontally
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2-3 Accelerator pixel size. 1: 8bit, 2: 15/16bit, 3: (2000) 32bit
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4 Causes lockup ??
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5 ??
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6-7 Clock Select bit 2-3. Bits 0-1 are in 3C2h/3CCh bits 2-3.
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3C4h index 12h (R/W):
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bit 0-1 Size of the linear frame buffer. 0: 64Kb, 1: 1Mb, 2: 2Mb, 3: 4Mb
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2 Set in high res text modes, clear in all other modes
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3-7 ??
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3C4h index 13h W(R/W):
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bit 0-15 Linear Address of Aperture bits 16-31.
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3C4h index 15h (R/W):
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bit 0-4 Write Bank in 64K units
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3C4h index 16h (R/W):
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bit 0-4 Read Bank in 64K units
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3C4h index 17h (R/W):
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bit 0-2 Pixels per scanline ?. 0: 640, 1: 800, 2: 1024, 4: 1280
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3C4h index 18h (R/W):
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bit 0-2 (1000) Display FIFO threshold level (0-7).
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(2000) Display FIFO threshold level bits 1-3. The display FIFO is
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32 levels deep on the 2000PV. Bits 0 & 4 of the threshold are in
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bits 5&7 of this register.
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3 If set enables the full 8 level display FIFO
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5 (2000) Display FIFO threshold level bit 4.
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7 (2000) Display FIFO threshold level bit 0.
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3C4h index 19h (R/W):
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bit 0-7 ??
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7 Set for VESA bus, clear for PCI bus.
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3C4h index 1Ah (R/W):
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bit 0-7 Scratch ??
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3C4h index 1Bh (R/W):
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bit 0-7 Scratch ??
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3C4h index 1Ch (R/W):
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bit 0-1 Clock ??
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2 Blanks display if set ?
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3-4 Pixel type: 0: 16c planar (or text), 1: 8bpp, 2: 15/16bpp, 3: 24bpp
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5-7 ??
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3C4h index 1Dh (R/W):
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bit 0 Set to enable access to extended registers.
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3C4h index 1Eh (R/W):
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bit 0-7 Scratch ??
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3C4h index 1Fh (R/W):
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bit 0-7 Scratch ??
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3C4h index 20h (R/W):
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bit 0 If set horizontally enlarges the cursor by a factor of 2 (15/16bpp).
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1 If set horizontally enlarges the cursor by a factor of 3 (24/32bpp).
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2 Set for 64x64 cursor, clear for 32x32 cursor.
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3 Enable the hardware cursor if set
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4 Selects Windows style cursor if clear, X11 style if set ?
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3C4h index 21h (R/W):
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bit 0-3 Cursor X position bits 8-11, lower 8 bits are in index 22h
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3C4h index 22h (R/W):
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bit 0-7 Cursor X position bits 0-7, upper 4 bits are in index 21h
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3C4h index 23h (R/W):
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bit 0-3 Cursor Y position bits 8-11, lower 8 bits are in index 24h
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3C4h index 24h (R/W):
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bit 0-7 Cursor Y position bits 0-7, upper 4 bits are in index 23h
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3C4h index 25h (R/W):
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bit 0-5 Selects the location of the hardware cursor map in video memory.
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63 = last 256 bytes of 2Mb video memory
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The cursor definition map is a 32x32 or 64x64 bitmaps stored as a
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a sequence of 16bit words, each word defines 8 pixels. Bits 0 & 8
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defines the leftmost pixel, bits 7 & 15 the rightmost.
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Low bit: High bit: Result (Windows):
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0 0 Cursor Color 1
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1 0 Screen data
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0 1 Cursor Color 0
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1 1 Inverse screen (XOR cursor)
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3C4h index 26h (R/W): "Cursor Color 0 low"
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bit 0-7 Cursor Color 0. Palette index in palette modes, in direct color modes
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the low byte of the 2 or 3 bytes pixel.
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3C4h index 27h (R/W): "Cursor Color 0 middle"
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bit 0-7 The 2nd byte of the 2 or 3 bytes Color 0 pixel
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3C4h index 28h (R/W): "Cursor Color 0 high"
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bit 0-7 The high byte of the 3 bytes Color 0 pixel in 24bit modes
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3C4h index 29h (R/W): "Cursor Color 1 low"
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bit 0-7 Cursor color 1. Palette index in palette modes, in direct color modes
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the low byte of the 2 or 3 bytes pixel.
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3C4h index 2Ah (R/W): "Cursor Color 1 middle"
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bit 0-7 The 2nd byte of the 2 or 3 bytes Color 1 pixel
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3C4h index 2Bh (R/W): "Cursor Color 1 high"
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bit 0-7 The high byte of the 3 bytes Color 1 pixel in 24bit modes
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3C4h index 2Ch (R/W):
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bit 0-5 Cursor X Hotspot.
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3C4h index 2Dh (R/W):
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bit 0-5 Cursor Y Hotspot.
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3CBh (R):
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bit 0-3 Number of FIFO slots free ??
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6 Set when engine busy ??
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3d4h index 29h (R/W):
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bit 0-2 ??
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3d4h index 30h
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bit 0 If set ??
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1-2
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3d4h index 31h (R/W):
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bit 0 Causes wraps if set ?
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1 ??
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2 If set doubles each scan line vertically
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3-4 ??
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5 If set causes a one pixel shift to the right.
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3d4h index 40h (R/W): Extended Horizontal CRTC Timings
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bit 0-2 Display Start Address bit 16-18. Bits 0-15 are in 3d4h index 0Ch,0Dh
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3 ?
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4 Vertical Retrace Start bit 10. Bits 0-7 are in 3d4h index 10h.
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5 Vertical Blank Start bit 10. Bits 0-7 are in 3d4h index 15h.
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6 Vertical Display End bit 10. Bits 0-7 are in 3d4h index 12h.
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7 Vertical Total bit 10. Bits 0-7 are in 3d4h index 06h.
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3d4h index 41h (R/W): Extended Vertical CRTC Timings
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bit 3 CRTC Offset bit 8. Bits 0-7 are in 3d4h index 13h.
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4 Horizontal Retrace Start bit 8. Bits 0-7 are in 3d4h index 04h
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5 Horizontal Blank Start bit 8. Bits 0-7 are in 3d4h index 02h
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6 Horizontal Display End bit 8. Bits 0-7 are in 3d4h index 01h
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7 Horizontal Total bit 8. Bits 0-7 are in 3d4h index 00h.
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3d4h index 42h (R/W): Interlace Retrace
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bit 0-7 In interlaced modes should be ~half of Horizontal Total.
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3d4h index 43h (R/W):
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bit 0-1 Same as index 40h bit 0-1 ??
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2
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3 If set display wraps at 256K
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4-7 ??
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3d4h index 44h (R/W): VGA Enhancement Register
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bit 0 Disables RAMDAC access
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1 ??
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2 If set the display is interlaced
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3-7 ??
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3d4h index 45h (R/W):
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bit 0-3 ??
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3d4h index 46h (R/W): Pixel Clock Control
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bit 2 (2000) If set 16 bits are sent to the DAC per pixel clock
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3-5 ??
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6 Inverts the pixel clock if set.
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7 ??
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3d4h index 50h (R):
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bit 3-7 Chip ID. 11h for the 1000VL, 12h for the 1000PV, 13h for the 2000PV
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The ARK can memory map the accelerator registers at A8000h:
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M+00h W():
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M+02h W():
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bit 0-? Drawing Style. 0: Solid, 1: Dashed, 2: Dotted, 3: DotDash,
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4: DashDotDot
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M+08h W():
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bit 0-? Fill Color ??
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M+0Ah W():
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M+18h W():
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bit 8-11 ROP. 0: Black (0), 1: Dest AND Src, 2: Src AND (NOT Dest), 3: Src,
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4: Dest AND (NOT Src), 5: Dest, 6: Dest XOR Src, 7: Src OR Dest,
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8: NOT (Src OR Dest), 9: NOT (Dest XOR Src), 10: NOT Dest, 11: Src
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OR (NOT Dest), 12: NOT Src, 13: Dest AND (NOT Src), 14: NOT (Dest
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XOR Src), 15: White (1)
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M+1Ah W()
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bit 0-15 Set to FFFFh ?? Write mask ??
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M+50h W(): Bresenham Error Term.
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bit 0-? 2*min(deltaX,deltaY)-max(deltaX,deltaY)
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M+54h W(): Bresenham Constant 1
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bit 0-? 2*min(deltaX,deltaY)
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M+56h W(): Bresenham Constant 2
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bit 0-? 2*min(deltaX,deltaY)-2*max(deltaX,deltaY)
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M+58h W():
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bit 0-15 Cliping Rect - Left Border. Lowest X coordinate drawn
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M+5Ah W():
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bit 0-15 Cliping Rect - Top Border. Lowest Y coordinate drawn
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M+5Ch W():
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bit 0-15 Cliping Rect - Right Border. Highest X coordinate drawn
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M+5Eh W():
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bit 0-15 Cliping Rect - Bottom Border. Highest Y coordinate drawn
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M+60h W():
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M+62h W():
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M+68h W():
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M+6Ch W():
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bit 0-2 X index into 8x8 pattern ?
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3-5 Y index into 8x8 pattern ?
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6- ??
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9-10 Both set ??
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or ?
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bit 0-15 Starting Source X coordinate
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M+6Eh W():
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bit 0-15 Starting Source Y coordinate
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M+70h W():
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bit 0-15 Starting X coordinate
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M+72h W():
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bit 0-15 Starting Y coordinate
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M+74h W():
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bit 0-? For line draw: Number of pixels drawn, for BitBlts the area width in
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pixels (-1 ?)
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M+76h W():
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bit 0-? For BitBlts the number of lines in the blt area (-1 ?)
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M+7Ch D():
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bit 16 Linedraw: Set if abs(deltaY) < deltaX
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17 Linedraw: Set if EndY < StartY
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18 Linedraw: Set if EndX < StartX
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21 Set for Line draw
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24 Set for ?? source
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28 Set for linedraw
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29 Set for BitBlt
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bit 4 or 26 set if source is a Pattern ??
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bit 8,9,12 or 23 set if source data is from CPU ??
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Modes:
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24h T 132 25 16 ()
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26h T 132 43 16 ()
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27h T 132 50 16 ()
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31h G 800 600 16 PL4
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32h G 1024 768 16 PL4
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33h G 1280 1024 16 PL4
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40h G 640 480 256 P8
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41h G 800 600 256 P8
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42h G 1024 768 256 P8
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43h G 1280 1024 256 P8
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44h G 1600 1280 256 P8
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4Fh G 640 400 256 P8
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50h G 640 480 32K P15
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51h G 800 600 32K P15
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52h G 1024 768 32K P15
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54h G 640 480 64K P16
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55h G 800 600 64K P16
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56h G 1024 768 64K P16
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58h G 640 480 16M P24
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59h G 800 600 16M P24
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