483 lines
20 KiB
Plaintext
483 lines
20 KiB
Plaintext
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There are two configuration methods, depending on the PCI chipsets used:
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Configuration Type 1:
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CF8h D(R/W):
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bit 0-7 Index into the configuration space to read/write at CFCh
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11-15 Card ID (0 - 31)
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16-19 PCI Bus ID (0 - 15)
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31 Set to enable the PCI bus configuration space
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CFCh D(R/W):
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bit 0-31 The index register identified by the PCI bus/card ID/Index in CF8h
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can be accessed here.
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Configuration Type 2:
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CF8h (R/W):
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bit 7 Set to select the PCI configuration space
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CFAh (R/W):
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bit 0-? Bus select ?
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Finding the PCI devices:
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PCItype:=0;
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outp($CF8,0);
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outp($CFA,0);
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if (inp($CF8)=0) and (inp($CFA)=0) then PCItype:=2
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else begin
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tmp=inpl($CF8);
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outpl($CF8,$80000000);
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if inpl($CF8)=$80000000 then PCItype:=1;
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outpl($CF8,tmp);
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end;
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case PCItype of
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1:begin {PCI type 1}
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for i:=0 to 511 do
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begin
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outpl($CF8,$80000000+i*longint(2048));
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tmp:=inpl($CFC);
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if ((tmp and $FFFF)<>$FFFF) and ((tmp shr 16)<>$FFFF) then
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_PCI Device: Vendor: (l and $FFFF) Device: (l shr 16)_
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end;
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end;
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2:begin {PCI type 2}
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outp($CF8,$80);
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outp($CFA,0); {Bus select?}
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for i:=0 to 15 do
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begin
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tmp:=inpl(i*256 +$C000);
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if ((tmp and $FFFF)<>$FFFF) and ((tmp shr 16)<>$FFFF) then
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_PCI Device: Vendor: (l and $FFFF) Device: (l shr 16)_
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end;
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outp($CF8,0);
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end;
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end;
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The PCI BIOS interface requires a 386 or better CPU.
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--------X-1AB001-----------------------------
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INT 1A - ? PCI ? - INSTALLATION CHECK
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AX = B001h
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Return: CF clear if installed
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DX = 4350h ('CP')
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CX = 2049h (' I')
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--------X-1AB002-----------------------------
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INT 1A - ? PCI ? - FIND PCI DEVICE
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AX = B002h
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CX = device ID
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DX = vendor ID
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SI = device index (0-n)
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Return: CF clear if successful
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BH = bus number
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BL = device/function number (bits 7-3 device, bits 2-0 func)
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--------X-1AB00A-----------------------------
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INT 1A - ? PCI ? - READ CONFIGURATION DWORD
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AX = B00Ah
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BH = bus number
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BL = device/function number (bits 7-3 device, bits 2-0 function)
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DI = register number (0000h-00FFh)
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Return: CF clear if successful
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CX = Low 16 bit of the DWORD
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DX = High 16 bit of the DWORD
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--------X-1AB101-----------------------------
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INT 1A - Intel PCI BIOS v2.0c - INSTALLATION CHECK
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AX = B101h
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Return: AH = 00h if installed
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CF clear
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EDX = 20494350h (' ICP')
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EDI = physical address of protected-mode entry point (see #0528)
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AL = PCI hardware characteristics (see #0527)
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BH = PCI interface level major version (BCD)
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BL = PCI interface level minor version (BCD)
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CL = number of last PCI bus in system
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EAX, EBX, ECX, and EDX may be modified
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all other flags (except IF) may be modified
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Note: this function may require up to 1024 byte of stack; it will not enable
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interrupts if they were disabled before making the call
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Bitfields for PCI hardware characteristics:
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Bit(s) Description (Table 0527)
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0 configuration space access mechanism 1 supported
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1 configuration space access mechanism 2 supported
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2-3 reserved
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4 Special Cycle generation mechanism 1 supported
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5 Special Cycle generation mechanism 2 supported
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6-7 reserved
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(Table 0528)
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Call protected-mode entry point with:
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registers as for real/V86-mode INT call
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CS = ring 0 descriptor with access to full address space
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Return: as for real/V86-mode call
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--------X-1AB102-----------------------------
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INT 1A - Intel PCI BIOS v2.0c - FIND PCI DEVICE
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AX = B102h
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CX = device ID
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DX = vendor ID
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SI = device index (0-n)
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Return: CF clear if successful
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CF set on error
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AH = status
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00h successful
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BH = bus number
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BL = device/function number (bits 7-3 device, bits 2-0 func)
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83h bad vendor ID
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86h device not found
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EAX, EBX, ECX, and EDX may be modified
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all other flags (except IF) may be modified
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Notes: this function may require up to 1024 byte of stack; it will not enable
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interrupts if they were disabled before making the call device ID FFFFh
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may be reserved as a wildcard in future implementations the meanings of
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BL and BH on return were exchanged between the initial drafts of the
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specification and final implementation all devices sharing a single
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vendor ID and device ID may be enumerated by incrementing SI from 0
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until error 86h is returned
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--------X-1AB103-----------------------------
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INT 1A - Intel PCI BIOS v2.0c - FIND PCI CLASS CODE
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AX = B103h
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ECX = class code (bits 23-0)
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SI = device index (0-n)
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Return: CF clear if successful
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CF set on error
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AH = status
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00h successful
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BH = bus number
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BL = device/function number (bits 7-3 device, bits 2-0 func)
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86h device not found
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EAX, EBX, ECX, and EDX may be modified
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all other flags (except IF) may be modified
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Notes: this function may require up to 1024 byte of stack; it will not enable
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interrupts if they were disabled before making the call the meanings
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of BL and BH on return were exchanged between the initial drafts of
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the specification and final implementation all devices sharing the
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same Class Code may be enumerated by incrementing SI from 0 until
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error 86h is returned
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--------X-1AB106-----------------------------
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INT 1A - Intel PCI BIOS v2.0c - PCI BUS-SPECIFIC OPERATIONS
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AX = B106h
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BL = bus number
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EDX = Special Cycle data
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Return: CF clear if successful
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CF set on error
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AH = status
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00h successful
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81h unsupported function
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EAX, EBX, ECX, and EDX may be modified
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all other flags (except IF) may be modified
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Note: this function may require up to 1024 byte of stack; it will not enable
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interrupts if they were disabled before making the call
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--------X-1AB108-----------------------------
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INT 1A - Intel PCI BIOS v2.0c - READ CONFIGURATION BYTE
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AX = B108h
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BL = device/function number (bits 7-3 device, bits 2-0 function)
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BH = bus number
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DI = register number (0000h-00FFh)
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Return: CF clear if successful
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CL = byte read
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CF set on error
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AH = status
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00h successful
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87h bad register number
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EAX, EBX, ECX, and EDX may be modified
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all other flags (except IF) may be modified
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Notes: this function may require up to 1024 byte of stack; it will not enable
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interrupts if they were disabled before making the call the meanings
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of BL and BH on return were exchanged between the initial drafts of
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the specification and final implementation
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--------X-1AB109-----------------------------
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INT 1A - Intel PCI BIOS v2.0c - READ CONFIGURATION WORD
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AX = B109h
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BL = device/function number (bits 7-3 device, bits 2-0 function)
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BH = bus number
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DI = register number (0000h-00FFh)
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Return: CF clear if successful
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CX = word read
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CF set on error
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AH = status
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00h successful
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87h bad register number
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EAX, EBX, ECX, and EDX may be modified
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all other flags (except IF) may be modified
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Notes: this function may require up to 1024 byte of stack; it will not enable
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interrupts if they were disabled before making the call the meanings
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of BL and BH on return were exchanged between the initial drafts of
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the specification and final implementation
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--------X-1AB10A-----------------------------
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INT 1A - Intel PCI BIOS v2.0c - READ CONFIGURATION DWORD
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AX = B10Ah
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BH = bus number
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BL = device/function number (bits 7-3 device, bits 2-0 function)
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DI = register number (0000h-00FFh)
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Return: CF clear if successful
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ECX = dword read
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CF set on error
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AH = status
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00h successful
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87h bad register number
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EAX, EBX, ECX, and EDX may be modified
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all other flags (except IF) may be modified
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Notes: this function may require up to 1024 byte of stack; it will not enable
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interrupts if they were disabled before making the call the meanings of
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BL and BH on return were exchanged between the initial drafts of the
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specification and final implementation
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--------X-1AB10B-----------------------------
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INT 1A - Intel PCI BIOS v2.0c - WRITE CONFIGURATION BYTE
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AX = B10Bh
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BH = bus number
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BL = device/function number (bits 7-3 device, bits 2-0 function)
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DI = register number (0000h-00FFh)
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CL = byte to write
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Return: CF clear if successful
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CF set on error
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AH = status
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00h successful
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87h bad register number
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EAX, EBX, ECX, and EDX may be modified
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all other flags (except IF) may be modified
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Notes: this function may require up to 1024 byte of stack; it will not enable
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interrupts if they were disabled before making the call the meanings
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of BL and BH on return were exchanged between the initial drafts of
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the specification and final implementation
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--------X-1AB10C-----------------------------
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INT 1A - Intel PCI BIOS v2.0c - WRITE CONFIGURATION WORD
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AX = B10Ch
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BH = bus number
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BL = device/function number (bits 7-3 device, bits 2-0 function)
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DI = register number (multiple of 2 less than 0100h)
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CX = word to write
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Return: CF clear if successful
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CF set on error
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AH = status
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00h successful
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87h bad register number
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EAX, EBX, ECX, and EDX may be modified
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all other flags (except IF) may be modified
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Notes: this function may require up to 1024 byte of stack; it will not enable
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interrupts if they were disabled before making the call the meanings
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of BL and BH on return were exchanged between the initial drafts of
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the specification and final implementation
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--------X-1AB10D-----------------------------
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INT 1A - Intel PCI BIOS v2.0c - WRITE CONFIGURATION DWORD
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AX = B10Dh
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BH = bus number
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BL = device/function number (bits 7-3 device, bits 2-0 function)
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DI = register number (multiple of 4 less than 0100h)
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ECX = dword to write
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Return: CF clear if successful
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CF set on error
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AH = status
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00h successful
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87h bad register number
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EAX, EBX, ECX, and EDX may be modified
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all other flags (except IF) may be modified
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Notes: this function may require up to 1024 byte of stack; it will not enable
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interrupts if they were disabled before making the call the meanings
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of BL and BH on return were exchanged between the initial drafts of
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the specification and final implementation
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--------X-1AB181-----------------------------
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INT 1A - Intel PCI BIOS v2.0c - INSTALLATION CHECK (32-bit)
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AX = B181h
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Return: as for AX=B101h
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--------X-1AB182-----------------------------
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INT 1A - Intel PCI BIOS v2.0c - FIND PCI DEVICE (32-bit)
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AX = B182h
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CX = device ID
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DX = vendor ID
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SI = device index (0-n)
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Return: as for AX=B102h
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--------X-1AB183-----------------------------
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INT 1A - Intel PCI BIOS v2.0c - FIND PCI CLASS CODE (32-bit)
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AX = B183h
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ECX = class code (bits 23-0)
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SI = device index (0-n)
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Return: as for AX=B103h
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--------X-1AB186-----------------------------
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INT 1A - Intel PCI BIOS v2.0c - PCI BUS-SPECIFIC OPERATIONS (32-bit)
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AX = B186h
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BL = bus number
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EDX = Special Cycle data
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Return: as for AX=B106h
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--------X-1AB188-----------------------------
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INT 1A - Intel PCI BIOS v2.0c - READ CONFIGURATION BYTE (32-bit)
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AX = B188h
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BL = bus number
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BH = device/function number (bits 7-3 device, bits 2-0 function)
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DI = register number (0000h-00FFh)
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Return: as for AX=B108h
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--------X-1AB189-----------------------------
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INT 1A - Intel PCI BIOS v2.0c - READ CONFIGURATION WORD (32-bit)
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AX = B189h
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BL = bus number
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BH = device/function number (bits 7-3 device, bits 2-0 function)
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DI = register number (0000h-00FFh)
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Return: as for AX=B109h
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--------X-1AB18A-----------------------------
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INT 1A - Intel PCI BIOS v2.0c - READ CONFIGURATION DWORD (32-bit)
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AX = B18Ah
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BL = bus number
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BH = device/function number (bits 7-3 device, bits 2-0 function)
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DI = register number (0000h-00FFh)
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Return: as for AX=B10Ah
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--------X-1AB18B-----------------------------
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INT 1A - Intel PCI BIOS v2.0c - WRITE CONFIGURATION BYTE (32-bit)
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AX = B18Bh
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BL = bus number
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BH = device/function number (bits 7-3 device, bits 2-0 function)
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DI = register number (0000h-00FFh)
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CL = byte to write
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Return: as for AX=B10Bh
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--------X-1AB18C-----------------------------
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INT 1A - Intel PCI BIOS v2.0c - WRITE CONFIGURATION WORD (32-bit)
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AX = B18Ch
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BL = bus number
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BH = device/function number (bits 7-3 device, bits 2-0 function)
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DI = register number (multiple of 2 less than 0100h)
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CX = word to write
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Return: as for AX=B10Ch
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--------X-1AB18D-----------------------------
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INT 1A - Intel PCI BIOS v2.0c - WRITE CONFIGURATION DWORD (32-bit)
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AX = B18Dh
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BL = bus number
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BH = device/function number (bits 7-3 device, bits 2-0 function)
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DI = register number (multiple of 4 less than 0100h)
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ECX = dword to write
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Return: as for AX=B10Dh
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The PCI configuration space consists of 256bytes per device, the first 64
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bytes are laid out as follows, though an adapter may not implement all fields.
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Offset Size Description:
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00h WORD Vendor ID. FFFFh is reserved.
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02h WORD Device ID. FFFFh is reserved.
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04h WORD System Bus Command
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Bit 0 I/O Space. If set the device is allowed to respond to
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I/O requests, if clear the device does not respond.
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1 Memory Space. If set the device is allowed to respond
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to Meory requests, if clear the device does not
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respond.
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3 Special Cycles. If set the device is allowed to monitor
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special cycles.
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5 VGA Palette Snoop. If set special snooping behavior is
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enabled. The device must not respond to DAC writes.
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If clear palette accesses are treated normally.
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6 Parity Error. If set the device responds to parity
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errors, if clear it ignores them. The device must
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generate parity even if this bit is clear.
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7 Wait Cycle Control. If set data/address stepping is
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enabled, disabled if clear.
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8 System Error Driver. If set the error driver reports
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parity errors, if clear the system error driver is
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disconnected.
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9 Back-to-Back Cycle. If set the device supports back-to
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-back cycles.
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06h WORD System Bus Status
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Bit 7 (R) Fast back-to-back. If set the device is capable of
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fast back-to-back cycles, if clear it is not.
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8 Bus Master. Only implemented by Bus Masters
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9-10 (R) Device Select Timing. DEVSEL# timing. 0: fast,
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1: medium, 2: slow
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11 Device Target-abort. Set whenever the device (as target)
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issues a Target Abort. Write 1 to reset.
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12 Received Target-abort. Set whenever the device (as
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Master) receives a Target Abort. Write 1 to reset.
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13 Master Abort Status. Set whenever the device issues a
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Master Abort. Write 1 to reset.
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08h BYTE Revision Code.
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09h BYTE Programming Interface.
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0Ah WORD Class. 300h for VGA devices, 1 for 8514/A devices
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0Ch BYTE Cache line size
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0Dh BYTE Latency timer.
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Bit 0-2 (R)
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3-7
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0Eh BYTE Header type
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Bit 0-6 Current offset for configuration register ?
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7 Multifunction Device?
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0Fh BYTE Bist?
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10h DWORD Base0 - Defines a Memory or I/O region used by the device
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Bit 0 (R) Memory or I/O. Set if the region is in I/O space,
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clear if it is in Memory space.
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1-2 (R) Locatable Area. 0: Anywhere in 32bit address space
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1: Below 1MB, 2: anywhere in 64bit address space
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3 (R) Pre-fetchable. Set if memory is cacheable, clear
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if not.
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4-7 (R) Address space size
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8-31 Memory Base. Upper 24bit of the base address.
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14h DWORD Base1 - Similar to Base0
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18h DWORD Base2 - Similar to Base0
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1Ch DWORD Base3 - Similar to Base0
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20h DWORD Base4 - Similar to Base0
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24h DWORD Base5 - Similar to Base0
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28h DWORD Reserved
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2Ch DWORD Reserved
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30h DWORD ROM Base - Defines the location & size of the BIOS ROM
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Bit 0 ROM BIOS Decode. Set to enable BIOS access
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11-14 (R) ROM BIOS Min Size.
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0: 32K ROM (bits 15-17 R/W)
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1: 64K ROM (bits 15 RO, 16-17 R/W)
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2: 128K ROM (bits 15-16 RO, 17 R/W)
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3: 256K ROM (bits 15-17 RO)
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15-31 BIOS Base Address. Upper 14-17 bits of the BIOS
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location. Depending on the BIOS size in bits 11-14
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the lowest 1/2/3 bits may be forced to 0.
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34h DWORD Reserved
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38h DWORD Reserved
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3Ch BYTE Interrupt Line
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Used for Interrupt Line info during initialisation
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3Dh BYTE Interrupt Pin
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Identifies the interrupt lines used
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3Eh BYTE Minimum Grant
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Specifies the longest burst allowed
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3Fh BYTE Max Lat
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Indicates how often the device geta access to the PCI bus.
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Known Vendor/Device ID combinations:
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Vendor: Device: Card:
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0E11h 3032h Compaq QVision 1280P
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1000h NCR
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1002h 4158h ATI Mach32 (68800-AX)
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4758h ATI Mach64 (88800-GX)
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1005h 2301h Avance Logic ALG2301
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2302h Avance Logic ALG2302
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2364h Avance Logic ALG2364
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100Ch 3202h Tseng ET4000/W32p revA
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3207h Tseng ET4000/W32p revD
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100Eh 9001h Weitek Viper/PCI
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9100h Weitek Viper Pro/SE
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1011h Digital
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1013h 00A0h Cirrus Logic CL-GD5430
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00A8h Cirrus Logic CL-GD5434
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1200h Cirrus Logic CL-GD7542 (Nordic)
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1202h Cirrus Logic CL-GD7543 (Viking)
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1204h Cirrus Logic CL-GD7541 (Nordic Light)
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101Ah NCR
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1023h 9420h Trident TGUI9420DGi
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9430h Trident TGUI9430
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1025h 1435h Acer Labs M1435 (huh maybe M3145??)
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102Bh 0518h Matrox ?
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0D10h Matrox Impression Plus
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102Ch 00B8h Chips&Tech CT64310
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00D8h Chips&Tech CT65545
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105Dh 2309h Number Nine (#9) Imagine-128
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1060h UMC
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1142h 3210h Alliance Pro Motion 3210
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1A08h 0000h Sierra 15064 ?
|
|
5333h 8811h S3 Trio64
|
|
8880h S3 86c866
|
|
88B0h S3 86c928P
|
|
88C0h S3 86c864
|
|
88C1h S3 86c864P
|
|
88D0h S3 86c964
|
|
EDD8h A091h ARK 1000PV
|
|
A099h ARK 2000PV
|