539 lines
20 KiB
Plaintext
539 lines
20 KiB
Plaintext
Trident SuperVGA
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Trident TVGA8800BR 512k Only 128K banks.
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TVGA8800CS 512k Has 64k banks and old/new mode
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TVGA8900B 1MB
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TVGA8900C 1MB
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TVGA8900CL 2MB
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TVGA8900D 2MB Same as 8900CL, but with a few bug corrected
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(which?)
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TVGA9000 Low component version
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TVGA9000i Low component count. 15/16 bit DAC on chip
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Clock generator on chip
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9200CXr 2MB
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TGUI9400CXi 2MB Clock & 24bit DAC onchip
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TGUI9420DGi 2MB As 9400, but with Accelerator (BitBlt, Color Exp
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Fills, Line draw and Linear Frame buffer)
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TGUI9430 As 9420 + Hardware cursor
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TGUI9440AGi 2MB As 9430, 16bit DAC interface and programmable
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clock ??
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TGUI9660XGi 64bit video memory path
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TGUI9680 As 9660, but with video acc
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LCD9100B Suppose these are LCD controllers, anyone seen them?
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LCD9100
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LX8200
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Support chips:
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TCK9001 Clock chip for the 8900B.
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Supplies: 25.175, 28.322, 44.9, 36, 57.272, 65, 50.35, 40 MHz
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TCK9002 Clock chip for the 8900C and later.
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Supplies: 25.175, 28.322, 44.9, 36, 57.272, 65, 50.35, 40,
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88, 98, 118.8, 108 MHz
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TCK9004 Clock chip for the 8900CL and later.
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Supplies: 25.175, 28.322, 44.9, 36, 57.272, 65, 50.35, 40,
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88, 98, 118.8, 108, 72, 77, 80, 75 MHz
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TKD8001 "ColorSync" truecolor RAMDAC
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What are the specs for all the new chips?? (CX,CXi,CL,CXr,GUI...)
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The Trident 8800 chips have a problem with 256 color modes,
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as they always double the pixels output in 256 color mode.
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Thus a 640x400 256 color mode (5Ch) actually uses a 1280x400
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frame, requiring at least a multi sync monitor.
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This problem is fixed on the 8900.
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Apparently Trident BIOS version 3.xx or later on a 8900C will support Sierra
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HiColor DACs (SC11483 or SC11487). No check is made for the existence of such
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a DAC, the mode is just set as if it was present, resulting in 1024x480,
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1280x480 and 1600x600 256color modes if an ordinary DAC is installed.
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100h W(R/W?): Microchannel ID low/high
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bit 0-15 Card ID bit 0-15
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3C3h (R/W): Microchannel Video Subsystem Enable Register:
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bit 0 Enable Microchannel VGA if set
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3C4h index 0Bh (R): Chip Version
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bit 0-7 Chip ID
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1 = TR 8800BR
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2 = TR 8800CS
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3 = TR 8900B
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4 = TVGA8900C
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13h = TVGA8900C
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23h = TR 9000
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33h = TVGA8900CL, TVGA8900D or TVGA 9000C
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43h = TVGA9000i
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53h = TR 9200CXr
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63h = TLCD9100B
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73h = TGUI9420
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83h = TR LX8200
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93h = TGUI9400CXi
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A3h = TLCD9320
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C3h = TGUI9420DGi
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D3h = TGUI9660XGi
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E3h = TGUI9440AGi
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F3h = TGUI9430 One source says 9420 ??
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The 63h, 73h, 83h, A3h and F3h entries are still in doubt.
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Note: Writing to index Bh selects old mode registers.
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Reading from index Bh selects new mode registers.
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Note: Writing to this register in order to force old mode registers
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should be done with two 8bit writes, not one 16bit write.
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3C4h index 0Ch (R/W): Power Up Mode Register 1
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bit 0 Fast Decode if set, Slow if clear
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1 (9000 & LCD9100) If clear 0 Wait states,
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if set bit 6 determines number of wait states.
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4 If set enable post port at 3C3h, at 46E8h if clear
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5 (8900C) If set enables access to upper 512KB in non-paged modes
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Must be clear in text and CGA modes.
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(9000 & LCD9100) If set uses 2 DRAMs, 4 if clear
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6 (9000 & LCD9100) If bit 1 is clear this bit determines the number
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of wait states. If set 2 Wait states, 1 if clear.
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5-6 (88xx and 89xx) 0=256K chip, 1 = 2 DRAMs, 2 = 4 DRAMs, 3 = 8 DRAMs.
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7 If set VRAM bus setting is 16, 8 if clear
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Note: This register can only be changed if New Mode Control 1 (3C4h index 0Eh)
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bit 7 is set
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3C4h index 0Dh (R/W): Old Mode Control 2
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bit 0-2 Emulation mode
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0=VGA, 3=EGA, 5=CGA,MDA,Hercules
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4 Enable Paging mode if set. If set the CRTC offset (3d4h index 13h)
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should be multiplied by 2, and the Display Start Address (3d4h index
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0Ch & 0Dh + 1Eh bit 5 and 3C4h Old Mode index 0Eh bit 0) is in units
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of 8 bytes rather than 4 (256 color modes only).
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5 DRAM clock enabled if set.
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3C4h index 0Dh (R/W): New Mode Control 2 (not 8800BR)
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bit 0 Clock Select bit 2. Bits 0-1 are in 3CCh bits 2-3.
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Clock table:
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0: 25.1 75 1: 28.322 2: 44.9 3: 36
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4: 57.272 5: 65 6: 50.35 7: 40
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8: 88 9: 98 10: 118.8 11: 108
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12: 72 13: 77 14: 80 15: 75
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For the 8800 and 8900B only the first 8 clocks are available.
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For the 9000i line 3 is: 8: 25.175, 9: 28.322, 10: 62.3, 11: 44.9
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1-2 Divide pixel clock by: 0=1, 1=2, 2=4, 3=1.5
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6 (9xxx) Clock Select bit 3. See bit 0
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Note: The old/new Mode Control 1/2 registers are selected by
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reading and writing the Chip version register (index Bh).
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3C4h index 0Eh (R/W): Old Mode Control 1
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bit 0 (8900 Only) CRTC Address bit 17. Apparently this determines in which
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part of memory the display is, as the display can not cross this
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line, but can be on either side. Note that in Paged Mode (3C4h Old
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Mode index 0Dh bit 4 is set) this bit has no effect as 17 bits can
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span the entire 1MB range.
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1-2 128kb Bank number (0-3)
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3 16 bit video interface if set
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4 (8900C, CL, CXr, GUI9420) Clock Select bit 3.
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See New mode 3C4h index Dh bit 0.
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3C4h index 0Eh (R/W): New Mode Control 1 (not 8800BR)
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bit 0-3 64k Bank nbr. When writing to this field XOR with 02h, when reading
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from this field no XOR is needed. This is used for Trident detection.
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In planar modes bits 0 and 2 form a two bit field.
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4-6 Reserved
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7 Must be set to update index 0Ch ???
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Note: The old/new Mode Control 1/2 registers are selected by
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reading and writing the Chip version register (index Bh).
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3C4h index Fh (R/W): Power-up Mode 2
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bit 0-3 Switch settings
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4 Bus type
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5 If set I/O address are at 3xxh, else at 2xxh.
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6 Enable ON-Card ROM if set
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7 16 bit ROM access enabled if set
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3CEh index 0Eh (R/W): New Source Address Register (8900CL/D,9200 +)
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bit 0-3 Bank register. If 3CEh index Fh bit 2 is clear and bit 0 is set this
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is the read bank and 3C4h index Eh the write register. Note that bit
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1 is inverted like 3C4h index Eh bit 1.
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3CEh index 0Fh (R/W): Miscellaneous Extended Functions (8900CL/D,9200 +)
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bit 0 DUAL. If set selects dual bank mode with separate read and write
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bank registers. If bit 2 is set 3D9h is the read bank and 3D8h the
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write bank, if bit 2 is clear 3CEh index Eh is the read bank and 3C4h
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index Eh the write bank
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3D8h is the combined read/write bank. Only active if bit 2 is set.
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1 When set the packed pixel modes (256 or more colors) uses bits 0-1 of
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the PEL panning register (3C0h index 13h) for single pixel horizontal
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scrolling rather than bits 1-2 (as Standard VGA).
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2 ENALTP. Set to use the alternative banking registers at 3D8h/3D9h,
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clear to use the old banking registers.
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?? Must be set when 3C4h index Ch bit 5 is set ??
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3 If set character clocks are 16pixels wide rather than 8
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3d4h index 1Eh (R/W): Module Testing Register
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bit 2 Vertical interlace if set
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In interlaced modes the CRTC offset (3d4h index 13h) is the number of
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bytes in TWO scanlines (NOT true for the 9440AGi!).
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Note that in interlaced modes the line doubling caused by index 9 bits
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0-4,7 is unlikely to work, as the (even,odd) linepair is repeated
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rather than each individual line causing stripes.
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3 If set Load fonts from Bottom, from top if clear
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4 If set the display wraps back to line 0 when the line counter reaches
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512.
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5 CRTC Display Start Address bit 16. Bits 0-15 are in 3d4h index Ch,Dh
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7 (not 88xx) Host address bit 16. If clear bit 5 has no effect.
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This does not affect 3C4h Old Mode index 0Eh bit 0.
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3d4h index 1Fh (R/W): Software Programming Register
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bit 0-1 (8800, 8900, 9000) Memory size 0=256k, 1=512k, 2=768k, 3=1M.
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0-2 (8900CL, 9200CXr, 94xx, 9660) Memory size 0=256k, 1=512k,
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2=768k, 3=1M, 4=256k, 5=512k, 6=768k, 7=2M.
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4-6 (9420DGi) Monitor Type.
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(9430,9440,9660) Monitor Type.
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Note: This register set by software
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Everex 8800 based cards have different layout, see below
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3d4h index 1Fh (R/W): Scratch Register (Everex 8800 Cards)
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bit 0 Paged memory mode in effect
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1 Memory size 0=256k, 1=512k
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2 Analog monitor attached
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3 44.9 MHz oscillator present
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Note: This register is set by software.
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3d4h index 21h (R/W): Configurable Linear Addressing Register (94xx)
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Bit 0-3 LAWB0-3. Bits 20-23 of the Linear Aperture address
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4 LAWS. If set the aperture is 2Mbytes, if clear 1MB.
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5 ENLA. Set to enable Linear aperture.
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6-7 Linear Aperture Address bits 24-25
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3d4h index 22h (R): CPU Latch Read Back
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bit 0-7 Data Latch value for current read plane.
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3d4h index 23h (R/W):
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bit 0-5 ??
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3d4h index 24h (R): Attribute State Read Back
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bit 0-6 Reserved
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7 Attribute Controller State
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If set the next write to 3C0h will go to the data
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register, if clear to the index register.
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3d4h index 26h (R): Attribute Index Read Back
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bit 0-7 Attribute Index Register value
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3d4h index 27h (R/W): (8900CL/D +)
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bit 0-1 Display Start Address bit 17-18. Bit 16 is in index 1Eh bit 5.
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3d4h index 28h (R/W):
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bit 0-7 ??
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3d4h index 29h (R/W): (8900CL/D +)
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bit 0 Connected to the RS2 input on the DAC ?.
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1 ??
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4 CRTC offset bit 8 ??
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3d4h index 2Ah (R/W):
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bit 6 ??
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3d4h index 2Fh
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bit 0-2 ?
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4 ?
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5-6 ?
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3d4h index 36h
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bit 1 ?
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7 ?
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3d4h index 38h (9440)
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bit 2-3 Pixel depth?. 1: 15/16 bit modes, 2: 24bit modes, 0: all other modes
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3d4h index 40h W(R/W): (9440)
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bit 0- Hardware Cursor *tal Location
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3d4h index 42h W(R/W): (9440)
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bit 0- Hardware Cursor *tal Location
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3d4h index 44h W(R/W): (9440)
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bit 0- Location of hardware cursor map in video memory in units of 1Kb
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The hardware cursor map appears to be a 32x32x2 or 64x64x2 bitmap
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organised in lines of 8 or 16 bytes, each having first 4 bytes
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(32pixels) of AND data and then 4bytes XOR data (windows style).
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The cursor displayed also depends on the cursor style (3d4h index 50h
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bit 6).
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AND: XOR: Style: Resulting screen:
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0 0 0 Palette index 0 ?
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1 0 0 Screen data (Transparent cursor)
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0 1 0 Palette index 255 ?
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1 1 0 Inverted screen (XOR cursor)
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0 0 1 Screen data (Transparent cursor)
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1 0 1 Palette index 0 ?
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0 1 1 Screen data (Transparent cursor)
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1 1 1 Palette index 255 ?
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3d4h index 46h (R/W): (9440)
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bit 0-5 Cursor Horizontal hotspot. The position (in pixels from the left) of
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the cursor hotspot within the 32x32 or 64x64 map. The displayed cursor
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starts at the hotspot and ends 32/64 pixels from the left edge (i.e.
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it does not wrap to the next line).
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3d4h index 47h (R/W): (9440)
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bit 0-5
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3d4h index 50h (R/W): (9440)
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bit 0 Set for 64x64 cursor, clear for 32x32 cursor
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6 Clear for Cursor Style 0 (Windows?), set for Cursor Style 1 (X11?)
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7 Enable hardware cursor if set
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3D8h (R/W): Destination Segment Register (8900CL/D,9200 +)
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bit 0-4 Bank number in 64k units. If 3CEh index Fh bit 0 is set this is the
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write bank, if not the combined read/write bank.
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This register is only active if 3CEh index Fh bit 2 is set.
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3D9h (R/W): Source Segment Register (8900CL/D,9200 +)
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bit 0-4 If 3CEh index Fh bit 0 is set this is the read bank.
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This register is only active if 3CEh index Fh bit 2 is set.
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Note: Ferraro (in Programmer's Guide to... 3rd edition) documents the
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accelerator registers at 21xAh for the later Tridents, however so far
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I have been unable to verify this.
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43C6h W(R/W): Memory Clock (9440)
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bit 0-15 Selects the memory clock. 2C6h = 50MHz, 307h = 58MHz, 87h = 64MHz
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8Eh = 75MHz
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Note: 3C4h index Eh (new) bits 1 & 7 must be set to update this register
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43C8h W(R/W): Video Clock (9440)
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bit 0-15 Selects the video clock when 3C2/Ch bits 2-3 = 2.
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Note: 3C4h index Eh (new) bits 1 & 7 must be set to update this register
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46E8h (R): Video Subsystem Enable Register
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bit 3 Enable VGA if set
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The memory mapped registers appears to be mapped at BFF00h (how to enable
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them ?). Probably only exists on the 9440 and later (9420?)
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M+20h (R?)
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bit 5 Set when the graphics engine is busy?
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6 Set if ? Data transfers should wait for it to clear?
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7 Set when ?
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M+22h (R/W):
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bit 0-? 9 for non-8bit modes, 4 for 8bit modes (<=1024), 8 for other modes
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M+24h (R/W):
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bit 0-2 Write 1 to start a Blit, 4 to start a line draw ?
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M+27h (R/W):
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bit 0-7 Raster op (=Bits 16-23 of the Windows ROP3).
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M+28h W(R/W):
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bit 2 Set when using pattern ??
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5 Set when using pattern ??
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6 ??
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8 If set the Blit moves bottom-to-top (decreasing address), if clear
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it is top-to-bottom (increasing address).
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9 If set the Blit moves right-to-left (decreasing address), if clear
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it is left-to-right (increasing address).
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14 Set for solid fills ??
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M+2Bh (R/W):
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bit 0-2 Offset into the pattern ?
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M+2Ch W(R/W):
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bit 0- Background color
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M+30h W(R/W):
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bit 0- Foreground color
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M+34h W(R/W):
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bit 0-15 Address of ?pattern? in units of 64bytes
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M+38h W(R/W):
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bit 0- Destination starting X-coordinate
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M+3Ah W(R/W):
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bit 0- Destination starting Y-coordinate
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M+3Ch W(R/W):
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bit 0- Source starting X-coordinate
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M+3Eh W(R/W):
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bit 0- Source starting Y-coordinate
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M+40h W(R/W):
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bit 0- Width of the Blit area in pixels
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M+42h W(R/W):
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bit 0- Height of the Blit area in scanlines
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M+44h
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M+46h W(R/W):
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Bank selection:
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Trident VGAs (except 8800BR) can operate in 2 different modes:
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Old Mode, with a 128k window to display memory at A000h - BFFFh
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and New Mode, with a 64k window to display memory at A000h - AFFFh.
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Old/New mode is selected by reading/writing the Chip Version Register
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(3C4h index 0Bh).
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Each mode has its own registers at 3C4h index 0Dh and 0Eh.
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ID Trident VGA:
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wrinx($3C4,$B,0); {Force old_mode_registers}
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chp:=inp($3C5); {Read chip ID and switch to new_mode_registers}
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old:=rdinx($3C4,$E);
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outp($3C5,0);
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value:=inp($3C5) and $F;
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outp($3C5,old);
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if value=2 then
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begin
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outp($3C5,old xor 2);
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case chp of
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1:Trident TR8800BR;
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2:Trident TR8800CS;
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3:Trident TR8900;
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4,$13:Trident TR8900C;
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$23:Trident TR9000;
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$33:Trident TR8900CL or D;
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$43:Trident TR9000i;
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$53:Trident TR8900CXr
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$63:Trident LCD9100B;
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$83:Trident LX8200;
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$93:Trident TVGA9400CXi
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$A3:Trident LCD9320;
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$73,$F3:Trident GUI9420;
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end;
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end
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else if (chp=1) and testinx2($3C4,$E,6) then
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Trident TVGA 8800BR {Haven't tested this yet}
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Video Modes:
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50h T 80 30 16 (8x16)
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51h T 80 43 16 (8x11)
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52h T 80 60 16 (8x8)
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53h T 132 25 16 (8x14)
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54h T 132 30 16 (8x16)
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55h T 132 43 16 (8x11)
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56h T 132 60 16 (8x8)
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57h T 132 25 16 (9x14)
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58h T 132 30 16 (9x16)
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59h T 132 43 16 (9x11)
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5Ah T 132 60 16 (9x8)
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5Bh G 800 600 16 PL4
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5Ch G 640 400 256 P8
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5Dh G 640 480 256 P8
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5Eh G 800 600 256 P8 (Undocumented on 8800)
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5Fh G 1024 768 16 PL4
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60h G 1024 768 4 8900 Only
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61h G 768 1024 16 PL4
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62h G 1024 768 256 P8 8900 Only
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63h G 1280 1024 16 PL4 Which chip/BIOS rev ?
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64h G 1280 1024 256 P8 8900CL only
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6Ah G 800 600 16 PL4 Newer boards
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6Bh G 320 200 16m P24 TVGA9000i+
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6Ch G 640 480 16m P24 8900CL+
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6Dh G 800 600 16m P24 8900CL+
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|
70h G 512 480 32K P15 89xx with Sierra DAC
|
|
71h G 512 480 64K P16 89xx with Sierra DAC
|
|
74h G 640 480 32K P15 89xx with Sierra DAC
|
|
75h G 640 480 64K P16 89xx with Sierra DAC
|
|
76h G 800 600 32K P15 89xx with Sierra DAC
|
|
77h G 800 600 64K P16 89xx with Sierra DAC
|
|
78h G 1024 768 32K P15 8900CL with Sierra DAC
|
|
79h G 1024 768 64K P16 8900CL with Sierra DAC
|
|
7Eh G 320 200 32K P15 TVGA9000i
|
|
7Fh G 320 200 64K P16 TVGA9000i
|
|
|
|
ZyMOS POACH51 modes:
|
|
|
|
60h G 960 720 16 PL4
|
|
61h G 1280 640 16 PL4
|
|
62h G 512 512 256 P8
|
|
63h G 720 540 16 PL4
|
|
64h G 720 540 256 P8
|
|
6Ah G 800 600 16 PL4
|
|
|
|
|
|
Everex Viewpoint use Everex modes.
|
|
|
|
|
|
Note: The TVGA9000i has an on-chip DAC with 32k/64k capability.
|
|
The BIOS on the card I have (BIOS version D3.51) doesn't
|
|
seem to handle the Hi/True color modes correctly.
|
|
I have managed to get the 320x200 32k/64k modes working by programming
|
|
the DAC command register directly, but the 512x480 modes and the 320x200
|
|
16m mode still doesn't work
|
|
|
|
|
|
|
|
Bios extensions:
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|
|
|
----------1000-------------------------------
|
|
INT 10 - VIDEO - SET VIDEO MODE
|
|
AH = 00h
|
|
AL = mode number
|
|
Return: AH = Status of call: (Trident Super VGA Chips)
|
|
|
|
Trident 8800 Trident 8900
|
|
00h Successful do
|
|
80h Fail. Wrong switch do
|
|
81h Insufficient Video do
|
|
Memory.
|
|
82h The 36MHz crystal Mode not supported
|
|
cannot support the mode
|
|
83h The 40MHz crystal Mode not supported
|
|
cannot support the mode.
|
|
84h The 44.9MHz crystal Mode not supported
|
|
cannot support the mode.
|
|
85h Dead or no crystal
|
|
86h Wrong CRTC base for dual screen
|
|
87h Text mode not supported
|
|
Note: The return code appears to be unsupported on some newer Trident
|
|
card, i.e. 9440AGi
|
|
----------1012-BL11------------------------------
|
|
INT 10 - VIDEO - Trident BIOS - Get BIOS Info
|
|
AH = 12h
|
|
BL = 11h
|
|
Return: AL = 12h if function supported
|
|
ES:BP -> BIOS info structure:
|
|
Offset: Size: Description:
|
|
00h BYTE ??? (=0)
|
|
01h BYTE OEM Code (00h for original Trident)
|
|
02h WORD ID ?? (1073h for 8800BR, 1074h for 8800CS,
|
|
1090h for 8900C or 9000i
|
|
04h 8 BYTEs BIOS date ('mm/dd/yy')
|
|
0Ch WORD ???
|
|
0Eh 8 BYTEs BIOS Version (' C3-128 ', ' C3-129 ',
|
|
' D3.51 ').
|
|
----------1012-BL12------------------------------
|
|
INT 10 - VIDEO - Trident BIOS - GET VIDEO RAM SIZE
|
|
AH = 12h
|
|
BL = 12h
|
|
Return: AL = 12h if function supported
|
|
AH = number of 256K banks of RAM installed
|
|
----------101200-BL14----------------------------
|
|
INT 10 - VIDEO - Trident LOCKFIFO - Get FIFO state
|
|
AX = 1200h
|
|
BH = 14h
|
|
Return: CX = FIFO state
|
|
Note: Implemented by the LOCKFIFO.COM utility
|
|
----------101201-BL14----------------------------
|
|
INT 10 - VIDEO - Trident LOCKFIFO - Get FIFO state
|
|
AX = 1201h
|
|
BH = 14h
|
|
CX = FIFO state (0..FFh, FFh = disabled)
|
|
Note: Implemented by the LOCKFIFO.COM utility
|