Dodajem knjige
This commit is contained in:
@@ -0,0 +1,500 @@
|
||||
Video 7 Super VGA.
|
||||
Bought by Headland Technologies in
|
||||
Bought by SPEA Software AG in 1993.
|
||||
|
||||
The earliest V7/Headland boards use Chips&Technologies and Cirrus chips.
|
||||
|
||||
|
||||
G2 GC205 VRAM-I/VGA-16 boards ?. Also known as HT 208 rev 1-3 ??
|
||||
G2 GC208 V7 1024i boards. Also known as HT208. Split banks
|
||||
HT 209 V7VRAM-II boards
|
||||
HT 216 Color expansion. RAster ops.
|
||||
HT 216-32 Local bus version of HT216 ?
|
||||
|
||||
|
||||
Board: Chip: Features:
|
||||
|
||||
VGA-16
|
||||
VRAM I Hardware Cursor
|
||||
VRAM II HT-208 rev B,C or D Split Bank
|
||||
VGA16 HT-216
|
||||
1024i HT-216
|
||||
|
||||
|
||||
|
||||
100h (R/W?): Microchannel ID low
|
||||
bit 0-7 Card ID bit 0-7
|
||||
|
||||
101h (R/W?): Microchannel ID high
|
||||
bit 0-7 Card ID bit 8-15
|
||||
|
||||
102h (R/W): Alt Video Subsystem Enable
|
||||
bit 0 Enable Video if set. Must be armed by 3C4h index 0FCh bit 7
|
||||
or in setup mode (46E8h bit4) to change.
|
||||
|
||||
3C2h (W): Misc Output register
|
||||
bit 5 Bit 1 of Bank no.
|
||||
Note: This register can be read at 3CCh.
|
||||
|
||||
3C3h (R/W): Video Subsystem Enable
|
||||
bit 0 Enable Microchannel Video if set
|
||||
Must be armed by 3C4h index 0FCh bit 7 to change.
|
||||
|
||||
3C4h index 6 (R/W): Extension Control
|
||||
bit 0 (R) Extensions enabled if set
|
||||
bit 0-7 (W) 0EAh Enables extensions, 0AEh disables.
|
||||
|
||||
3C4h index 7 (R/W): Reset Horizontal Character Counter
|
||||
|
||||
3C4h index Bh (R/W): CA1 ??
|
||||
bit 0 If set the CA1 port is an output with the state from bit 1,
|
||||
if clear the port is an input. The state is returned in bit 1.
|
||||
1 Data pin for CA1. Usually connected to 8/6 pin on DAC
|
||||
Note: Some sort of access to index 0D0h is needed to enable the port.
|
||||
|
||||
3C4h index 80h (R/W): Test
|
||||
|
||||
3C4h index 81h (R/W): Test
|
||||
|
||||
3C4h index 82h (R/W): Test
|
||||
|
||||
3C4h index 83h (R/W): Attribute Control Index
|
||||
|
||||
3C4h index 8Eh W(R): Chip Version
|
||||
bit 0-15 Chip version. Index 8Fh is the major version, and 8Eh is the minor.
|
||||
Originally this was probably for two different chips.
|
||||
8xxxh-FFFFh VEGA VGA Chip
|
||||
70xxh HT208 chip rev. 1,2 or 3 (VRAM I/VGA-16)
|
||||
7070h G2 GC205
|
||||
714xh HT208 chip rev A (VRAM II ?). Also G2 GC208.
|
||||
7151h HT208 chip rev B (VRAM II)
|
||||
7152h HT208 chip rev C or D (VRAM II)
|
||||
7760h HT216 rev B or C
|
||||
7763h HT216 rev B, C or D (huh ??)
|
||||
7764h HT216 rev E
|
||||
7765h HT216 rev F
|
||||
|
||||
3C4h index 94h (R/W): Pointer Pattern Address
|
||||
bit 0-7 Start address of the Pointer Pattern. This value selects the 256 byte
|
||||
block within the last 64k of the 256k block selected by index 0FFh
|
||||
bits 5-6.
|
||||
The cursor map consists of two 32x32 bitmaps. The first is the AND
|
||||
mask and the second is the XOR mask.
|
||||
AND XOR
|
||||
0 0 Black
|
||||
0 1 Inverse screen data
|
||||
1 0 Screen data
|
||||
1 1 White
|
||||
|
||||
3C4h index 9Ch (R/W): Pointer Horizontal Position High
|
||||
bit 0-2 Bit 8-10 of the X co-ordinate of the Cursor
|
||||
|
||||
3C4h index 9Dh (R/W): Pointer Horizontal Position Low
|
||||
bit 0-7 Bit 0-7 of the X co-ordinate of the Cursor
|
||||
|
||||
3C4h index 9Eh (R/W): Pointer Vertical Position High
|
||||
bit 0-1 Bit 8-9 of the Y co-ordinate of the Cursor
|
||||
|
||||
3C4h index 9Fh (R/W): Pointer Vertical Position Low
|
||||
bit 0-7 Bit 0-7 of the Y co-ordinate of the Cursor
|
||||
|
||||
3C4h index A0h (R/W): GC Memory Latch 0
|
||||
bit 0-7 Plane 0 Memory Latch Data
|
||||
|
||||
3C4h index A1h (R/W): GC Memory Latch 1
|
||||
bit 0-7 Plane 1 Memory Latch Data
|
||||
|
||||
3C4h index A2h (R/W): GC Memory Latch 2
|
||||
bit 0-7 Plane 2 Memory Latch Data
|
||||
|
||||
3C4h index A3h (R/W): GC Memory Latch 3
|
||||
bit 0-7 Plane 3 Memory Latch Data
|
||||
|
||||
3C4h index A4h (R/W): Clock Select
|
||||
bit 2-4 Clock select bit 0-2. Bit 3 is in index F8h bit 0
|
||||
This is activated when 3C2h is written. Actually 3C2h/3CCh bits 2-3
|
||||
will override bits 2-3 of this register
|
||||
HT208-A (in MHz) generates:
|
||||
0: 25.175, 1: 48.6, 2: 22.9, 3: 0
|
||||
4: 34, 5: 48.6, 6: 22.9, 7: 0
|
||||
8: 25.175, 9: 28.322, 10: 22.9, 11: 0
|
||||
12: 34, 13: 36, 14: 22.9, 15: 40
|
||||
Another card gives (8-15 unknown):
|
||||
0: 25.175, 1: 28.322, 2: 30.000, 3: 32.514
|
||||
4: 34.000, 5: 36.000, 6: 38.000, 7: 40.000
|
||||
|
||||
3C4h index A5h (R/W): Cursor Attributes
|
||||
bit 0 Cursor blink enabled if clear
|
||||
3 Text Cursor Mode is XOR if set, Replace if clear
|
||||
7 Hardware Graphics Cursor Enabled if set
|
||||
|
||||
3C4h index B3h (R/W): Scratch RAM
|
||||
bit 0-7 Scratch
|
||||
|
||||
3C4h index B4h (R): Power On Reset 0 (HT216)
|
||||
|
||||
3C4h index B5h (R): Power On Reset 1 (HT216)
|
||||
|
||||
3C4h index B6h (R): Power On Reset 2 (HT216)
|
||||
|
||||
3C4h index B7h (R): Power On Reset 3 (HT216)
|
||||
|
||||
3C4h index C0h (R/W): Monochrome Lock
|
||||
|
||||
3C4h index C1h (R/W):
|
||||
bit 0 Set to enable 8bit DAC rather than 6bit.
|
||||
|
||||
3C4h index C8h (R/W): Miscellaneous Control 2
|
||||
bit 0 Set to enable MOVSB operation ?? (HT216 only?)
|
||||
4 Set in Extended 256 color modes
|
||||
6 Enable Linear Addressing if set
|
||||
|
||||
3C4h index C9h (R/W): Extended Linear Address Offset
|
||||
bit 0-3 Bits 20-23 of the Linear Address Offset
|
||||
|
||||
3C4h index CAh (R/W): Horizontal Overflow (HT216)
|
||||
|
||||
3C4h index CBh (R/W): Low Water Mark (HT216)
|
||||
|
||||
3C4h index CCh (R/W): DM Function Control (HT216)
|
||||
|
||||
3C4h index CDh (R/W): Extended ALU Function Control (HT216)
|
||||
bit 0-1 Color Expansion mode:
|
||||
0,2: VGA compatible mode
|
||||
1: Packed pixel 8plane color expansion
|
||||
3: Planar color expansion mode
|
||||
2-3 Bit mask source. 0: Bitmask from 3CEh index 8
|
||||
1: Bit mask from CPU byte, 2,3: Bit mask from 3C4h index F5h
|
||||
5 If set RMW cycles are enabled.
|
||||
6 If set enables Source to Destination alignment.
|
||||
7 Set to Enable Raster Operations
|
||||
|
||||
3C4h index CEh (R/W): Extended ALU Function Select (HT216)
|
||||
bit 0-3 Raster Operation.
|
||||
0: Set to 0 ...
|
||||
|
||||
3C4h index CFh (R/W): Extended Linear Address Offset High (HT216)
|
||||
bit 0-7 Bits 24-31 of the Linear Address Offset
|
||||
|
||||
3C4h index E0h (R/W): Miscellaneous Control (HT208 rev A +)
|
||||
bit 0 Interlaced
|
||||
5-6 Reserved
|
||||
7 Enables Split Bank Mode if set(VRAM II or HT216 only)
|
||||
On the HT208 rev A, split banks appears to cause index E8h to be the
|
||||
read/write bank register for A000h-A7FFh and index E9h to be the
|
||||
read/write bank register for A800h-AFFFh.
|
||||
|
||||
3C4h index E1h (R/W): Interlace Value
|
||||
|
||||
3C4h index E2h (R/W): Extended Character Width Enable
|
||||
|
||||
3C4h index E3h (R/W): High Water Mark
|
||||
|
||||
3C4h index E8h (R/W): Single/Write Bank Register (HT208 rev A +)
|
||||
bit 0-7 Single/Write Bank in units of 4KB.
|
||||
For 16color modes this is in units of 1KB.
|
||||
|
||||
3C4h index E9h (R/W): Read Bank Register (HT208 rev A +)
|
||||
bit 0-7 Read Bank in units of 4KB.
|
||||
Only Active if Split mode enabled (3C4h index E0h bit 7 set)
|
||||
|
||||
3C4h index EAh (W): Switch Strobe
|
||||
Note: A write to this register copies the switch positions to
|
||||
the Switch Readback Register (3C4h index F7h).
|
||||
|
||||
3C4h index EBh (R/W): Emulation Control
|
||||
|
||||
3C4h index ECh (R/W): Foreground Latch 0
|
||||
bit 0-7 Foreground Latch for plane 0. When in Dither Foreground mode
|
||||
(3C4h index FEh bit 2-3 = 2) the data in this register
|
||||
replaces the data written from the processor.
|
||||
|
||||
3C4h index EDh (R/W): Foreground Latch 1
|
||||
bit 0-7 Foreground Latch for plane 1.
|
||||
|
||||
3C4h index EEh (R/W): Foreground Latch 2
|
||||
bit 0-7 Foreground Latch for plane 2.
|
||||
|
||||
3C4h index EFh (R/W): Foreground Latch 3
|
||||
bit 0-7 Foreground Latch for plane 3.
|
||||
|
||||
3C4h index F0h (R/W): Fast Foreground Latch Load
|
||||
bit 0-7 The Foreground Latches (3C4h index ECh to EFh) for the four memory
|
||||
planes can be loaded by writing to this register. The writes will
|
||||
cycle through planes 0-3. A read will restart at plane 0.
|
||||
|
||||
3C4h index F1h (R/W): Fast Latch Load State
|
||||
bit 0-1 Background Latch Load State. Determines which of the four memory
|
||||
latches will be loaded by a write to 3C4h index F2h. Each write to
|
||||
index F2h will increment this value and each read from index F2h
|
||||
will reset it to 0.
|
||||
2-3 Unused
|
||||
4-5 Foreground Latch Load State. Determines which of the four Foreground
|
||||
latches (3C4h index ECh to EFh) will be loaded by the next write to
|
||||
3C4h index F0h. Each write to index F0h will increment this value
|
||||
and each read from index F0h will reset it to 0.
|
||||
6-7 Unused
|
||||
|
||||
3C4h index F2h (R/W): Fast Background Latch Load
|
||||
bit 0-7 The Memory Data Latches for the four memory planes can be loaded by
|
||||
writing to this register. The writes will cycle through planes 0-3.
|
||||
A read will restart at plane 0.
|
||||
|
||||
3C4h index F3h (R/W): Masked Write Control (Only with VRAM)
|
||||
bit 0 Enables Masked Writes if set
|
||||
1 If set rotated CPU byte is used as WriteMask, else Masked Write Mask
|
||||
register is used.
|
||||
|
||||
3C4h index F4h (R/W): Masked Write Mask (Only with VRAM)
|
||||
bit 0-7 If Masked Writes enabled (3C4h index F3h bit 0 set)
|
||||
Only the bits set here will be updated in Video memory.
|
||||
|
||||
3C4h index F5h (R/W): Foreground/Background Pattern
|
||||
bit 0-7
|
||||
|
||||
3C4h index F6h (R/W): 1MB RAM Bank Select
|
||||
bit 0-1 Write Bank no bit 2-3 if 256 color, bit 0-1 else.
|
||||
2-3 Read Bank no bit 2-3 if 256 color, bit 0-1 else.
|
||||
4-5 CRTC Bank (Address bit 16-17)
|
||||
6 Display address Wraps Around at bank boundary if clear
|
||||
7 Split Screen Wraps around at bank boundary if clear
|
||||
|
||||
3C4h index F7h (R/W): Switch Readback
|
||||
bit 0-7 Switch positions as read by the last write to the Switch
|
||||
Strobe Register (3C4h index EAh)
|
||||
|
||||
3C4h index F8h (R/W): Extended Clock Control
|
||||
bit 0 Clock select bit 3. Bits 0-2 are in index A4h bits 2-4.
|
||||
5-7 Clock Source: See index A4h bits 2-4.
|
||||
Note: depending on mode and other bits in this register other
|
||||
values may be selected.
|
||||
|
||||
3C4h index F9h (R/W): Page Select
|
||||
bit 0 bit 16 of Video Memory Address. (Only needed if in a
|
||||
256 color mode, and 3C4h index FCh bit 1-2 = 1).
|
||||
|
||||
3C4h index FAh (R/W): Extended Foreground Color
|
||||
bit 0-3 Foreground expansion color.
|
||||
Bit 0 is written to plane 0 et cetera.
|
||||
|
||||
3C4h index FBh (R/W): Extended Background Color
|
||||
bit 0-3 Background expansion color
|
||||
Bit 0 is written to plane 0 et cetera.
|
||||
|
||||
3C4h index FCh (R/W): Compatibility Control
|
||||
bit 0 Enable Extended Attribute functions if set
|
||||
Extended attributes allows underlining using a mask
|
||||
in plane 3 for each character.
|
||||
1 256-Color 64K/128K paging Select. 128K pages if set, 64K pages else.
|
||||
Only active if bit 2 set
|
||||
2 256-Color Paging Enabled if set.
|
||||
3-4 Reserved.
|
||||
5 Enables sequential chain4 mode if set ??
|
||||
6 Reserved.
|
||||
7 If set allows enabling VGA via 102h bit 0 or 3C3h bit 0.
|
||||
|
||||
3C4h index FDh (R/W): Extended Timing Select
|
||||
|
||||
3C4h index FEh (R/W): Foreground/Background Control
|
||||
bit 0 Unused
|
||||
1 Foreground/background source select
|
||||
Source is CPU data if set, 3C4h index F5h else.
|
||||
2-3 Foreground/background mode select
|
||||
0 Set/Reset Output (Standard VGA) mode
|
||||
1 Solid Color Expansion Mode
|
||||
A monochrome bitmap is expanded to color.
|
||||
For each bit of data written from the processor
|
||||
a zero bit causes the background color (3C4h index FBh)
|
||||
to be written in the corresponding pixel, and a 1 bit
|
||||
causes the ForeGround color (3C4h index FAh) to be written.
|
||||
2 Dithered ForeGround. The data from the processor is
|
||||
replaced by data from four Foreground Latches (3C4h index
|
||||
ECh to EFh). The normal VGA Read Latches function as normal.
|
||||
3 Uses Background Latch (transparent).
|
||||
4-7 Unused
|
||||
|
||||
3C4h index FFh (R/W): 16 bit Interface Control
|
||||
bit 0 16 bit memory if set
|
||||
1 16 bit I/O if set
|
||||
2 Fast Write Enabled if set
|
||||
3 16 bit ROM access if set
|
||||
4 Enable bank selection (Access to memory >256K) if set.
|
||||
5-6 Cursor Pattern Page Select
|
||||
Select which 256k bank the cursor pattern is in.
|
||||
7 (Read only) Card in 8 or 16 bit slot
|
||||
|
||||
3d4h index 1Fh (R): Identification register
|
||||
bit 0-7 Returns bit 0-7 of the Start Address High Register
|
||||
(3d4h index 0Ch) XORed with 0EAh.
|
||||
|
||||
3d4h index 22h (R): Graphics Controller Data Latch
|
||||
bit 0-7 Data from one of 4 bit-planes selected through the
|
||||
RMS field of the Read Map Select Register (3CEh index 4)
|
||||
|
||||
3d4h index 24h (R): Graphics Controller Data
|
||||
bit 0-4 Attribute Index. Same as 3C1 bit 0-4.
|
||||
5 Palette source. Same as 3C1h bit 5
|
||||
7 Does the Attribute Controller point to Index or Data .
|
||||
|
||||
3d4h index 30h-3Fh (W): Clear Vertical Display
|
||||
bit 0 if set speeds up video memory access by increasing the
|
||||
vertical Retrace Period.
|
||||
|
||||
|
||||
46E8h (W): ROM Map & Video Subsystem
|
||||
bit 0-2 Enable VGA PC/AT
|
||||
3 Enable VGA PC/AT if set
|
||||
4 Enter VGA Setup Mode if set
|
||||
In Setup Mode only registers 102h, 3C3h and 46E8h
|
||||
are active.
|
||||
|
||||
|
||||
4BC4h,4BC5 used.
|
||||
|
||||
|
||||
Bank Select:
|
||||
|
||||
Two methods exists:
|
||||
|
||||
All models can use method 1:
|
||||
For 2 and 4 color modes bit 16 of the address is in 3C2h bit 5.
|
||||
|
||||
For 16 color modes separate read and write banks can be selected
|
||||
through 3C4h index F6h.
|
||||
|
||||
For 256 color modes the bank fields in 3C4h index F6h select
|
||||
bit 18&19 of the video memory address.
|
||||
Bit 16 is selected through 3C4h index F9h bit 0.
|
||||
Bit 17 is selected through Miscellaneous Output Register
|
||||
(3C2h/3CCh bit 5).
|
||||
Bit 16&17 are shared by read and write operations.
|
||||
|
||||
For Version 4 (HT208-A) and above separate bank registers are available.
|
||||
Both read and write banks exists.
|
||||
|
||||
|
||||
ID Video 7 VGA Chip Set:
|
||||
|
||||
vio($6F00);
|
||||
if rp.bx=$5637 then
|
||||
begin
|
||||
vio($6F07);
|
||||
SubVers:=(rdinx($3C4,$8F) shl 8) + rdinx($3C4,$8E);
|
||||
case SubVers of
|
||||
$8000..$FFFF:VEGA_VGA;
|
||||
$7000..$70FF:HT208 version 1-3
|
||||
$7140..$714F:HT208 rev A;
|
||||
$7151:HT208 rev B
|
||||
$7152:HT208 rev CD
|
||||
$7760:HT216 rev BC
|
||||
$7763:HT216 rev D
|
||||
$7764:HT216 rev E
|
||||
$7765:HT216 rev F
|
||||
end;
|
||||
end;
|
||||
|
||||
|
||||
Video Modes:
|
||||
40h T 80 43 16
|
||||
41h T 132 25 16
|
||||
42h T 132 43 16
|
||||
43h T 80 60 16
|
||||
44h T 100 60 16
|
||||
45h T 132 28 16
|
||||
|
||||
60h G 752 410 16 PL4
|
||||
61h G 720 540 16 PL4
|
||||
62h G 800 600 16 PL4
|
||||
63h G 1024 768 2 PL1
|
||||
64h G 1024 768 4 PL2E
|
||||
65h G 1024 768 16 PL4
|
||||
66h G 640 400 256 P8 V1024 w/VRAM
|
||||
67h G 640 480 256 P8
|
||||
68h G 720 540 256 P8 VRAM only
|
||||
69h G 800 600 256 P8 VRAM only
|
||||
6Ah G 1024 768 256 P8
|
||||
70h G 1280 1024 16 PL4
|
||||
|
||||
|
||||
BIOS extensions:
|
||||
|
||||
----------106F00-----------------------------
|
||||
INT 10 - VIDEO - INSTALLATION CHECK (Video7 VGA,VEGA VGA)
|
||||
AX = 6F00h
|
||||
Return: BX = 5637h ('V7') indicates Video7 VGA/VEGA VGA extensions are present
|
||||
= 4850h ('HP') indicates HP Extended BIOS video functions present
|
||||
----------106F01-----------------------------
|
||||
INT 10 - VIDEO - Get Monitor Info (Video7 VGA,VEGA VGA)
|
||||
AX = 6F01h
|
||||
Return: AL = monitor type code (HP and VEGA VGA only) (values are for HP)
|
||||
00h non-HP card with ROM and possibly its own INT 10h driver
|
||||
41h MultiMode video display adapter
|
||||
45h standard monochrome display adapter
|
||||
46h standard color display adapter
|
||||
AH = status register information
|
||||
bit 0 = display enable
|
||||
0 = display enabled
|
||||
1 = vertical or horizontal retrace in progress
|
||||
bit 1 = light pen flip flop set
|
||||
bit 2 = light pen switch activated
|
||||
bit 3 = vertical retrace if set
|
||||
bit 4 = monitor resolution
|
||||
0 = high resolution (>200 lines)
|
||||
1 = low resolution (<=200 lines)
|
||||
bit 5 = display type
|
||||
0 = color
|
||||
1 = monochrome
|
||||
bits6,7= diagnostic bits
|
||||
CL = current value of Extended Control register
|
||||
(HP, and only if AL=41h)
|
||||
Note: bits 0-3 are the same as the EGA/VGA status register bits 0-3
|
||||
----------106F02-----------------------------
|
||||
INT 10 - VIDEO - HP Vectra (Video7 ?) - Set Monitor Info
|
||||
AX = 6F02h
|
||||
BL = new value for extended control register
|
||||
Bit 0 Screen resolution (0: 200 lines, 1: 400)
|
||||
1 Underline enable (if set 'blue' bit of ForeGround color is
|
||||
the underline bit)
|
||||
2 Font. 0: Standard-8, 1: HP-Roman-8
|
||||
3 Memory disabled for CPU access
|
||||
4 Allow access to full 32K memory rather than wrap at 16K
|
||||
5 Select 2nd 16K page rather than first
|
||||
Note: this function is only valid when an HP MultiMode Video Display Adapter
|
||||
is installed. The Extended Control register is at I/O address 3DDh
|
||||
----------106F03-----------------------------
|
||||
INT 10 - VIDEO - HP Vectra (Video7 ?) - Modify Monitor Info
|
||||
AX = 6F03h
|
||||
BH = Exclude mask (set bits are not modified)
|
||||
BL = new value for bits indicated in BH
|
||||
Result = ((old value) and BH) or ((not BH) and BL)
|
||||
Note: This function is only valid when an HP MultiMode Video Display Adapter
|
||||
is installed
|
||||
----------106F04-----------------------------
|
||||
INT 10 - VIDEO - Get Mode and Screen Resolution (Video7 VGA, VEGA VGA)
|
||||
AX = 6F04h
|
||||
Return: AL = current video mode (see AX=6F05h)
|
||||
BX = horizontal columns (text) or pixels (graphics)
|
||||
CX = vertical columns (text) or pixels (graphics)
|
||||
----------106F05-----------------------------
|
||||
INT 10 - VIDEO - Set Video Mode (Video7 VGA, VEGA EXTENDED EGA/VGA)
|
||||
AX = 6F05h
|
||||
BL = mode:
|
||||
00h-13h = standard IBM modes (see AH=00h)
|
||||
40h-6Ah = see table above.
|
||||
----------106F06-----------------------------
|
||||
INT 10 - VIDEO - SELECT AUTOSWITCH MODE (V7VGA,VEGA VGA)
|
||||
AX = 6F06h
|
||||
BL = Autoswitch mode select
|
||||
00h select EGA/VGA-only modes
|
||||
01h select Autoswitched VGA/EGA/CGA/MGA modes
|
||||
02h select 'bootup' CGA/MGA modes
|
||||
BH = enable/disable (00h enable, 01h = disable selection)
|
||||
----------106F07-----------------------------
|
||||
INT 10 - VIDEO - GET VIDEO MEMORY CONFIGURATION (V7VGA,VEGA VGA)
|
||||
AX = 6F07h
|
||||
Return: AL = 6Fh
|
||||
AH = bits 0-6 = number of 256K blocks of video memory
|
||||
bit 7 = DRAM/VRAM (0: DRAM, 1: VRAM)
|
||||
BH = chip revision (SR8F) (S/C Chip in VEGA VGA)
|
||||
BL = chip revision (SR8E) (G/A Chip in VEGA VGA)
|
||||
CX = 0000h
|
||||
Reference in New Issue
Block a user