Dodajem knjige
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UMC UM85c408 max 1MB
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UMC UM85c418 max 1MB. 32bit bus. IDE HD controller built in.
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Support chips:
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UM9502 Clock chip. Supplies 25.175, 27.8?, 36, 65.1, 44.9, 50, 80, 75 MHz
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UM70c178 High color 15/16 bit DAC (Similar to Sierra SC11487)
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3BFh (R/W):
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Note: written with ACh on startup ?
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3C4h index 5 (R/W):
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bit 5
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7
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3C4h index 6 (R/W):
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bit 0-3 Read bank in 64K units
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4-7 Write bank in 64K units
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3C4h index 7 (R/W):
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bit 0 Clock Select bit 2 (bits 0-1 are in 3C2h/3CCh bits 2-3)
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1
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2 If set memory access is 16bit, if clear 8bit.
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3
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4 If set the "blanked" lines flash a copy of the 1st ? line
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6-7 Video Memory: 0: 256K, 1: 512K, 2/3: 1MB
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Set by BIOS on initialisation.
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3C4h index 8 (R/W):
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bit 0 If set trashes display ?
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3 If set causes the first >200 pixels of each scanline to be blanked ??
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5 If set changes the order/way pixels are displayed:
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In 16 color modes each even byte is shown twice, causing the odd ones
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to be skipped.
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In "normal" 256color modes (3d4h index 33h bit 4 is clear), each even
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bank (64K) is shown twice, causing the odd ones to be skipped.
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In extended 256color modes (3d4h index 33h bit 4 is set) some strange
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pixel replication happens
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6 If set divides Video Clock by 2
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7 If clear disables bit 0 of the bank registers
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3C4h index 9 (R/W):
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bit 2 Causes drastic color shifts if set??
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3 Blanks display if set
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7 If set divides Video Clock by 2
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3C4h index 0Ah (R/W):
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3CEh index 9 (R/W):
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bit 1 If set causes flashing on the start of color blocks ??
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2 If set causes the image to be more crude (even pixels shown twice) ?
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3 Changes the order/way pixels are decoded within each byte/word/dword.
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3CEh index 0Ah (R/W): Scratch
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bit 0
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1
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2 If set HiColor is 64K, if clear 32K
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3 If set only use lowest 2 bits of each bank register
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4
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6
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7 If set only use lowest bit of the bank registers
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3CEh index 0Bh (R/W): Scratch
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bit 0-7 Current Video Mode
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3d4h index 2Eh (R/W):
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bit 3 If set doubles each scan line
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4 If set divides Video Clock by 3.5 ??
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5 ??
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7 ??
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3d4h index 2Fh (R/W):
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bit 0 Set if in an interlaced mode
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1 If set disables access to memory above 256K ?
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4-7 Affects the Clock selection ??
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3d4h index 33h (R/W):
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bit 0-1 Display Start Address bit 16-17
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4 If set the display wraps at 256K
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5 If set pixels are doubled both horizontally and vertically ??
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3d4h index 35h (R/W): (418 only)
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bit 0-3
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Set if in an extended 256color mode
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ID UMC superVGA:
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old:=inp($3BF);
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outp($3BF,3);
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if not testinx($3C4,6) then
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begin
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outp($3BF,$AC);
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if testinx($3C4,6) then UMC
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end;
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outp($3BF,old);
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Modes:
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46h T 132 25 2 (8x14)
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47h T 132 29 2 (8x12)
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48h T 132 32 2 (8x12)
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49h T 132 44 2 (8x8)
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50h G 640 480 32K P15/P16 !Note: 32K or 64K is selected
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51h G 800 600 32K P15/P16 !from 3CEh index Ah bit 2.
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58h T 80 32 16 (9x16)
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5Ch G 640 480 256 P8
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5Eh G 800 600 256 P8
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5Fh G 1024 768 16 PL4
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60h T 132 25 16 (8x14)
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61h T 132 29 16 (8x12)
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62h T 132 32 16 (8x12)
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63h T 132 44 16 (8x8)
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64h T 132 60 16 (8x8)
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6Ah G 800 100 16 PL4
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6Bh T 100 37 16 (8x16)
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6Ch G 800 600 256 P8
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72h T 80 60 16 (8x8)
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73h G 640 480 16 PL4
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74h T 80 66 16 (8x8)
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78h T 100 37 16 (8x16)
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79h G 800 600 16 PL4
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7Ah G 1280 1024 16 PL4
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7Dh G 512 512 256 P8
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7Eh G 640 400 256 P8
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7Fh G 1024 768 256 P8
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---------V-1012-A0----------------------------
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INT 10 - VIDEO - UMC - SET SCROLL TYPE
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AH = 12h
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BL = A0h
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AL = Type of scroll in text modes
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00h Jump (Sets 0:487h bit 6)
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01h Smooth (Clears 0:487h bit 6)
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---------V-102000-----------------------------
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INT 10 - VIDEO - UMC - GET BANKs
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AH = 2000h
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Return: AL = 20h if supported
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BL = Read bank
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BH = Write bank
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---------V-102001-----------------------------
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INT 10 - VIDEO - UMC - SET BANKs
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AH = 2001h
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BL = Read Bank
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BH = Write Bank
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Return: AL = 20h if supported
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