Dodajem knjige
This commit is contained in:
@@ -0,0 +1,539 @@
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Targa
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Targa+
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Usually the Targa+ operates in Non-Contigous mode where the 16 I/O registers
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used are spread in 4 groups of 4 registers each separated by 400h. By setting
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a jumper the Targa+ can operate in Contigous mode where the 16 registers are
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laid out sequentially. Also the base I/O address is set by jumpers.
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Note that this is one adapter where the indexed registers can really be 16bit
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wide, so that the notation W(R/W) indicates ONE 16bit index, not two 8bit ones
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Contiguous: Non-Contiguous: Read: Write:
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Reg00: + 00h + 0000h VIDSTAT COLOR0
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Reg01: + 01h + 0001h COLOR1
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Reg02: + 02h + 0002h CTL COLOR2
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Reg03: + 03h + 0003h MASKL COLOR3
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Reg04: + 04h + 0400h LBNK VIDCON
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Reg05: + 05h + 0401h READAD INDIRECT
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Reg06: + 06h + 0402h MODE1 HUESAT
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Reg07: + 07h + 0403h OVSTRT OVSTRT
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Reg08: + 08h + 0800h USCAN MASKL
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Reg09: + 09h + 0801h MASKH MASKH
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Reg10: + 0Ah + 0802h OSCAN LBNK
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Reg11: + 0Bh + 0803h HBNK HBNK
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Reg12: + 0Ch + 0C00h ROWC ROWC
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Reg13: + 0Dh + 0C01h MODE2 MODE2
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Reg14: + 0Eh + 0C02h RBL WBL
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Reg15: + 0Fh + 0C03h RBH WBH
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Reg00 (R): VIDSTAT
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bit 0 If set an odd field is being displayed if clear an even field.
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1 If clear a sync signal is detected indicating that an external video
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source is connected to the Targa+
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Reg00 (W): COLOR0
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bit 0-7 Low byte of the Border Color
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Note: this register is also accessible as ADV index E0h
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Reg01 (W): COLOR1
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bit 0-7 Second byte of the Border Color
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Note: this register is also accessible as ADV index E1h
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Reg01 (R): CTL
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bit 0 Set whenever a vertical blanking occurs. Cleared when this register
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is read
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1-3 The version number for the Targa chipset
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4-7 Memory configuration. Ah: T16, Bh: T16P, Eh: T16/32, Fh: T16/32P
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or T64
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Reg02 (W): COLOR2
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bit 0-7 Third byte of the Border Color.
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When in 16bit mode this should be set to 0.
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Note: this register is also accessible as ADV index E2h
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Reg03 (R): MASKL
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This is the read port for Reg08
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Reg03 (W): COLOR3
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bit 0-7 High byte of the Border Color.
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When in 16 or 24bit mode this should be set to 0
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Note: this register is also accessible as ADV index E3h
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Reg04 (R): LBNK
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This is the read port for Reg10
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Reg04 (W): VIDCON
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bit 0 LiveMixSrc. 0: Bilevel Blending, 1: Dynamic Blending
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1-5 Contrast. 10h is nominal
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6 Set if inputting from a RGB source, clear for Composite or S-video
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inputs.
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Note: This register is also present at Advanced index E4h.
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Reg05 (R): READAD
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bit 3 INAE. If set the Targa+ is in Advanced Operating Mode
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Note: This is the read port for the ADVANCED register (Std indirect 90h)
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Reg05 (W): INDIRECT
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bit 0-7 If the Targa+ is in Advanced Mode (the INAE bit is set) this is the
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index register for the Advanced registers.
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Write the index to this register and read/write the data at Reg14.
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Reg06 (R): MODE1
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This is the read port for Reg12
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Reg06 (W): HUESAT
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bit 0-4 Hue for input composite video. Nominal 10h
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5-7 Saturation for input composite video. Nominal 4
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Reg07 (R/W): OVSTRT
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bit 0-7 Used for standard Targa mode
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Reg08 (R): USCAN
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Reading this register places the Targa+ in underscan mode
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Reg08 (W): MASKL
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bit 0-7 Low mask byte. Each bit set will protect the corresponding bit(s) in
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memory from change during CPU access. This does not affect capture!
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Note: This register can be read from Reg03
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Reg09 (R/W): MASKH
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bit 0-7 High mask byte. Each bit set will protect the corresponding bit(s) in
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memory from change during CPU access. This does not affect capture!
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Reg10 (R): OSCAN
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Reading this register places the Targa+ in overscan mode
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Reg10 (W): LBNK
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bit 0-5 32K bank number for the lower half of the 64K window
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Note: This register can be read from Reg04
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Reg11 (R/W): HBNK
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bit 0-5 32K bank number for the upper half of the 64K window
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Reg12 (R): ROWCNT
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bit 0-7 This register is 0 when the display is in retrace, or else the number
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of the line currently being displayed
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Reg12 (W): MODE1
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bit 0 If set the video memory is enabled, if clear the video memory is
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disabled and can not be read or written.
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3-5 In Targa compatibility mode this selects one of eight 64K video
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memory blocks
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6 MOD. If clear the INDIRECT register (reg05) is an index to the
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advanced indirect registers. If set the INDIRECT register is an index
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to the standard indirect registers.
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Note: This register can be read from Reg06
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Reg13 (R/W): MODE2
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bit 2-3 ZOOM factor. 0: none, 1: x2, 2: x4, 3: x8
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4-5 DISPMODE.
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0: Display from memory with fixed color border
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1: Live video with fixed color border
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2: Overlay mode with live border
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3: Live mode with live border
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6 Enables the capture feature.
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7 GENLOCK. If set the Targa+ will attempt to sync to the clock supplied
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with the incoming video. If clear the Targa+ is in Master Mode and
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provides its own video timing control
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Reg14 W(R/W): RB/WB
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bit 0-15 Data port for the Advanced registers. The index is written to Reg05
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and the data is read or written in this register.
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Some of the Advanced registers are 8bits and some 16bits.
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ADV index 20h W(R/W): CLOCK
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bit 0-10 The 13.5MHz clock is divided by this value to get the line clock.
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I.e.. 858 gives 13.5MHz/858 = 15.734KHz (NTSC frequency).
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ADV index 21h (R/W): GENCTRL
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bit 0 Vertical Preload Mode. If set the vertical counter is reset every
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time the frame alignment is found to be false, if clear the vertical
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counter is reset only after 7 consecutive fields are found to be
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misaligned.
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1-2 Field. Selects the field which is used for frame alignment.
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0: Odd field, 1: Even field, 2: either field is used.
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3-5 (R) If bit 0 is clear, this is the number of consecutive
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misalignments which has happened.
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ADV index 40h W(R/W): VTOTAL
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bit 0-10 This is twice the number of lines in a field. If the value is odd,
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interlaced timing will be generated.
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11-15 Should be set to 0
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ADV index 41h W(R/W): HTOTAL
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bit 0-8 This is the number of SGCLK pulses in half a scanline
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9-15 Should be set to 0
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ADV index 42h W(R/W): SYNC
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bit 0-3 This is twice the number of scanlines used for vertical sync.
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4-7 Should be set to 0
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8-13 This is half the number of SGCLK pulses in one horizontal sync
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pulse.
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14-15 Should be set to 0
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ADV index 43h W(R/W): HPHASE
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bit 0-8 When the Targa+ is in Slave Genlock mode, this is the number of
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SGCLK pulses before a Horizontal Reference pulse is generated.
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Depending on bit 9 this is from the start or the middle of the line.
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9 If set the value in bits 0-8 is from the middle of the scanline,
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if clear it is from the beginning of the scanline.
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10-15 Should be set to 0
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ADV index 44h W(R/W): VBEND
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bit 0-10 This is twice the number of scanlines blanked for each field.
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11-15 Should be set to 0
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ADV index 45h W(R/W): HBSTRT
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bit 0-8 The number of SGCLK pulses from the middle of the scanline to the
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start of the Horizontal Blanking.
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9 Should be set to 1
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10-15 Should be set to 0
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ADV index 46h W(R/W): HBEND
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bit 0-8 The number of SGCLK pulses from the end of the scanline to the end
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of Horizontal Blanking.
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9-15 Should be set to 0
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ADV index 47h W(R/W): VSTRT
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bit 0-10 This is twice the scanline where display starts. If this value is
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larger than VEND (index 44h) a border is shown in the color defined
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by COLOR0-3 (Reg00-Reg03).
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11-15 Should be set to 0
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ADV index 48h W(R/W): VEND
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bit 0-10 This is twice the number of the scanline where display stops.
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If this value is smaller then VTOTAL (index 40h) a border is shown
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in the color defined by COLOR0-3 (Reg00-Reg03).
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11-15 Should be set to 0
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ADV index 49h W(R/W): HSTRT
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bit 0-9 The number of SGCLK pulses from the end of the scanline until
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display starts. If this value is larger than HBEND (index 46h) a
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border is shown in the color defined by COLOR0-3 (Reg00-Reg03).
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10-15 Should be 0
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ADV index 4Ah W(R/W): HEND
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bit 0-9 The number of SGCLK pulses from the middle of the scanline until the
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display stops. If this value is smaller then HBSTRT (index 45h) a
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border is shown in the color defined by COLOR0-3 (Reg00-Reg03).
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10-15 Should be 0
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ADV index 4Bh W(R/W): BURST
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bit 0-6 The number of SGCLK pulses from the start of Horizontal Blanking to
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the start of the color burst signal.
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7 Should be set to 0
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8-13 The width of the color burst in SGCLK pulses.
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14-15 Should be set to 0
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ADV index 4Ch W(R/W): SGCNTRL1
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bit 0-3 Delay for sync outputs in number of pixels. Typically 9.
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4-7 Delay for the composite blanking in number of pixels.
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Typically 5.
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8 Should be set to 0
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9 Number of refresh cycles per scan lines
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10-15 Should be set to 0
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ADV index 4Dh W(R/W): SGCNTRL2
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bit 0 Should be set to 0
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1 If set use Meander burst mode (PAL), if clear use normal burst mode
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(NTSC).
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2-3 The field generated when doing non-interlaced scanning.
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In normal burst mode (NTSC) 0: Even field, 1: Odd field.
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In Meander burst mode (PAL) 0: field0, 1: field1, 2: field2,
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3: field3
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4 If set the new sync generator is used for access to the new Targa+
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feature set, if clear the original sync generator is used for
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compatibility with the original Targa
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5 If set video display is enabled.
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6 If set video refresh is enabled.
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7 If set enables the sync outputs (Horizontal Sync, Vertical Sync,
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Composite Sync, Composite Blanking, Color Burst and half
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horizontal rate signal used for PAL). If clear these outputs are
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held in their inactive state.
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8-15 Should be set to 0
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ADV index 4Eh W(R/W): SGSTATUS
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bit 0-1 The current field being displayed.
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In normal burst mode (NTSC): 0: Even field, 1: Odd field
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In Meander burst mode (PAL):
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0: field0, 1: field1, 2: field2, 3: field3
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2 If set the Targa+ is producing vertical sync.
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3 The vertical drive signal
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4 If set the Targa+ is producing vertical sync.
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5-15 Should be set to 0
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ADV index 53h W(R/W): LINECNT
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bit 0-9 The number of the scanline being displayed.
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10-15 Should be set to 0
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Note: the lower 8 bits can also be read from the ROWCNT (Reg12) register.
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ADV index 80h W(R/W): TOP
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bit 0-9 This is display line the display wraps to when it reaches the line
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in BOT. In interlaced modes this is half the line number
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ADV index 81h W(R/W): BOT
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bit 0-9 When the display reaches this line it wraps to the line in TOP
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In interlaced modes this is half the line number
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ADV index 82h W(R/W): VPAN
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bit 0-9 This is the line number the display starts at for each field.
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This is coded as 511-(Physical row / 2)
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ADV index 84h (R/W): DSCAN
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bit 0 If clear the display is interlaced.
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1-6 Should be set to 0
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7 If the display is non-interlaced (bit 0 is set) this bit selects
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whether the first line displayed is from the odd or even bank.
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0: Odd, 1: Even
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ADV index 85h (R/W): CLOCKMODE
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bit 0-1 Clocking mode:
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0: Up to 512 pixels per scanline, interlaced. PCLK from 9.5 to
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11.5MHz. Can both display and capture.
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PCLK = SGCLK = SCLK = MCLK/4
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1: Up to 512 pixels per scanline, non-interlaced. PCLK from 19 to
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23MHz. Display only.
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PCLK = SCLK = MCLK/2, SGCLK = MCLK/4
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2: Hiresolution interlaced modes. PCLK from 11.5 to 13MHz and from
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13.5 to 15MHz. Can both display and capture.
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PCLK = SGCLK = MCLK/2, SCLK = MCLK/4
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3: Hiresolution non-interlaced modes. PCLK from 23 to 26MHz and
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from 27 to 30MHz. Display only.
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PCLK = MCLK, SGCLK = SCLK = MCLK/2
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2-3 Should be set to 0
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4 Set if in hiresolution modes (>512 pixels across).
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5-6 These bits must be preserved when writing this register
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7 Should be set to 0
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ADV index 90h (R/W): ADVANCED
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bit 0-1 Memory mode. 0: 8bit per pixel, 1: 16bit, 2: 24bit, 3: 32bit.
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2 Set in 16 and 32 bit modes except 16bit hiresolution modes.
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3 INAE. If set the Targa+ is in Advanced Operation mode, if clear in
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Standard Operation mode.
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4-5 Must be set to 0
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6 If set interrupts are active high, if clear active low.
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7 If set interrupts are enabled, if clear disabled.
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ADV index 91h (R/W): WAIT
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bit 0-1 Wait states for reads: 0: 1, 1: 2, 2: 4, 3: 0
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2-3 Wait states for writes: 0: 1, 1: 2, 2: 4, 3: 0
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4-5 Wait states for I/O ops: 0: 1, 1: 2, 2: 4, 3: 0
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6 DacClk. Clock signal for I2C bus. This bit should be preserved
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unless the I2C bus is being accessed.
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7 DacData. Data signal for I2C bus. This bit should be preserved
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unless the I2C bus is being accessed.
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ADV index 92h (R/W): CEM
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bit 0-3 ByCap. Each bit if set enables capture via one channel.
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Bit 0 is the Blue channel, bit 1 is the Green, bit 2 is the Red
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and bit 3 is the Alpha channel.
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ADV index A0h W(R/W): TAP
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bit 0-9 In Advanced Operating Mode this is the number of the first pixel
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displayed in each line. In DSCAN or Hires mode this is in units of
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two pixels
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ADV index A1h (R/W): MEMORY
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bit 0 Must be preserved.
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1-4 Video Memory base address:
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BigBank/Linear mode: Bank mode:
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0: illegal 80000h
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1: 100000h 90000h
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2: 200000h A0000h
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3: 300000h B0000h
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4: 400000h C0000h
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5: 500000h D0000h
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6: 600000h E0000h
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7: 700000h F0000h
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8: 800000h illegal
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9: 900000h illegal
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Ah: A00000h illegal
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Bh: B00000h illegal
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Ch: C00000h illegal
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Dh: D00000h illegal
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Eh: E00000h illegal
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Fh: F00000h illegal
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5-6 Memory addressing:
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0 Bank addressing
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2 BigBank addressing
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3 Linear Addressing
|
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7 If clear memory transfers are 16bit
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ADV index B0h W(R/W): BITCAP
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bit 0-15 Should be set to FFFFh. Reserved for future use.
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ADV index D0h (R/W): VGA
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bit 0 Set if each line is wider than 512 pixels.
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2 compareEnb. See index EAh bits 0-1.
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3-4 OverlayVGASrc. Determines the VGA overlay mode.
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0: VGA only, 1: TARGA+ only, 2: TARGA+ overlay (TARGA+ specifies
|
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overlay), 3: VGA overlay (VGA specifies overlay)
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5 MixLock. Used to lock the mixer in the off state.
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Should be set to 1 for compatibility with the original Targa.
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7 Diff8. If set the difference between the 8bit live signal and an
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8bit memory image is produced at the output of the mixer.
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ADV index D1h (R/W): COMP0
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bit 0-7 Low byte of the 24bit COMP register used in VGA and TARGA+ overlay
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compare
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ADV index D2h (R/W): COMP1
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bit 0-7 Middle byte of the 24bit COMP register used in VGA and TARGA+
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overlay compare. This byte is not used in 8bit modes
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ADV index D3h (R/W): COMP2/VGAMASK
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bit 0-7 High byte of the 24bit COMP register used in VGA and TARGA+
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overlay compare. This byte is only used in 24bit modes.
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This value is also used as a mask value for the TARGA+ and VGA 8bit
|
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overlay compare modes
|
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ADV index D8h (R/W): LUT WRITE
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bit 0-7 This is the write index into the RAMDAC palette. First write the
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index of the palette color to this register, then write three times
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to the LUT COLOR PALETTE register (index D9h) (red, green and then
|
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blue). When the blue data is written, this register is automatically
|
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incremented.
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This is functionally equivalent to the VGA register 3C8h
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ADV index D9h (R/W): LUT COLOR PALETTE
|
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bit 0-7 Palette data.
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This is functionally equivalent to the VGA register 3C9h
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ADV index DAh (R/W): LUT MASK
|
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bit 0-7 This value is anded with the color index before it reaches the
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palette chip.
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This is functionally equivalent to the VGA register 3C6h
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ADV index DBh (R/W): LUT READ
|
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bit 0-7 This is the read index into the RAMDAC palette. First write the
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index of the palette color to this register, then read three times
|
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from the LUT COLOR PALETTE register (index D9h) (red, green and then
|
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blue). When the blue data is read, this register is automatically
|
||||
incremented.
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||||
This is functionally equivalent to the VGA register 3C7h
|
||||
|
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ADV index DEh (R/W): LUT COMMAND
|
||||
bit 0-1 Selects the frequency band.
|
||||
2 Enables the sync generator if set. Should be set for proper
|
||||
operation.
|
||||
3 DacEnb. Should be set (1) for proper operation.
|
||||
4 Should be set (1).
|
||||
5 Selects whether a 0 IRE or 7.5 IRE blanking pedestal is used.
|
||||
Should be set to 0 for PAL signals.
|
||||
6-7 Should be set to 0.
|
||||
|
||||
ADV index E0h (R/W): COLOR0
|
||||
bit 0-7 Low byte of the Border Color
|
||||
Note: this register can also be written to at Reg00
|
||||
|
||||
ADV index E1h (R/W): COLOR1
|
||||
bit 0-7 Second byte of the Border Color
|
||||
Note: this register can also be written to at Reg01
|
||||
|
||||
ADV index E2h (R/W): COLOR2
|
||||
bit 0-7 Third byte of the Border Color
|
||||
Note: this register can also be written to at Reg02
|
||||
|
||||
ADV index E3h (R/W): COLOR3
|
||||
bit 0-7 High byte of the Border Color
|
||||
Note: this register can also be written to at Reg03
|
||||
|
||||
ADV index E4h (R/W): VIDCON
|
||||
bit 0 LiveMixSrc. 0: Bilevel Blending, 1: Dynamic Blending
|
||||
1-5 Contrast. 10h is nominal
|
||||
6 Set if inputting from a RGB source, clear for Composite or S-video
|
||||
inputs.
|
||||
Note: This register can also be written to at Reg04
|
||||
|
||||
ADV index E5h (R/W): LIVEMIXZERO
|
||||
bit 0-7 Used with the chromakeyer as an amplitude adjustment.
|
||||
The LIVEMIX control signal to the digital Blender is calculated as:
|
||||
(LiveMixIn - LIVEMIXZERO) << LiveMixGain
|
||||
LiveMixGain is bits 6-7 of the BUFFERPORT register
|
||||
|
||||
ADV index E6h (R/W): HUESAT
|
||||
Note: This register can also be written to at Reg06
|
||||
|
||||
ADV index E7h (R/W): SVIDEO
|
||||
bit 0-6 Should be set to 1
|
||||
7 SVHS. If VIDCON (ADV index E4h) bit 6 is clear this bit selects
|
||||
whether the input is a standard composite signal (0) or Svideo (1).
|
||||
Svideo means you have separate Y and C signals.
|
||||
|
||||
ADV index E8h (R/W): VIDEOMODE
|
||||
bit 0-1 BufferPortSrc. Only valid if index E9h bit 0 is 0.
|
||||
Determines the input to the Buffer Port Input of the Blender
|
||||
0: 8bits, 1: lower 16bits, 2: upper 16bits, 3: 24bits
|
||||
2-3 Which8. Selects the byte (Red, Green, Blue or Alpha) sent to the
|
||||
Blender Input 2 (in 8bit mode) or used as overlay control data (in
|
||||
32bit mode). 0: Blue, 1: Green, 2: Red, 3: Alpha
|
||||
4 MonoSrc. If bits 5-6 are 0 this selects the source of the monochrome
|
||||
capture. 0: green input channel, 1: Chromakeyer
|
||||
5-6 CM. TARGA+ capture mode: 0: Mono, 2: 16bit color, 3: 24bit color
|
||||
7 bbyp. If set the Blender is bypassed and the output to the DACs is
|
||||
directly from the VRAM
|
||||
|
||||
ADV index E9h (R/W): BUFFERPORT
|
||||
bit 0 BufferPortColor. If set the Buffer Port Input of the Blender is fed
|
||||
from the Border Color registers, if clear from VRAM
|
||||
1 LivePortColor. If set (and BLENDER1 bit 4 is set) the Live Port of
|
||||
the Blender receives bits 0-14 of the border color registers, rather
|
||||
than from VRAM
|
||||
2 LiveMixColor. If set, Color3 provides the LIVEMIX control signal
|
||||
3-4 LutByp. Contro9ls whether the output of the Blender is passed
|
||||
through or around the LUTs
|
||||
5 Alpha8. Data width of the Alpha channel. 8bit if set, 7 if clear.
|
||||
6-7 LiveMixGain. Shiftvalue for the alpha control values passed to the
|
||||
blender. 0: Normal, 1: Shift left 1 bit, 2: Shift left 2 bits.
|
||||
|
||||
ADV index EAh (R/W): MIXCTRL3
|
||||
bit 0-1 overlaySrc. Specifies the source of the overlay control signal.
|
||||
If index D0h bit 2 is set, the source is:
|
||||
0: 8bit masked compare, 2: 15/24 bit compare
|
||||
if clear, the source is:
|
||||
0: bit 15 of VRAM, 1: bit 31 of VRAM, 2: 0
|
||||
2 overlayInv. If set the overlay control data is inverted before being
|
||||
used.
|
||||
3 liveMixInv. If set the Alpha control signal is inverted before
|
||||
reaching the blender.
|
||||
4 CM3. If set the Targa+ recaptures the blended output from the
|
||||
blenders.
|
||||
5-7 Reserved. Should be set to 0
|
||||
|
||||
ADV index EBh (R/W): LIVEPORT
|
||||
bit 0-2 Reserved. Should be set to 0
|
||||
3 livePortWord. Only valid if bit 4 set and index E9h bit 1 is clear.
|
||||
If set the upper 16 bits of VRAM are sent to the blender, if clear
|
||||
the lower 16 bits are used
|
||||
4 livePortSrc. If set the blender is fed from the border color
|
||||
registers or from VRAM, if clear live data is fed to the blender.
|
||||
5 live8. Only active if bit 4 is set and
|
||||
6 fgp. Controls the ForeGround processor used in conjugation with the
|
||||
chromakeyer.
|
||||
7 Reserved. Should be set to 0
|
||||
|
||||
ADV index ECh (R/W): INVERT
|
||||
bit 0 ZeroBlue. If set the blue signal does not participate in the
|
||||
calculation of chroma signal
|
||||
1 Chroma. If set the chromaOut signal only depends on the blue input
|
||||
2-5 Should be set to 9
|
||||
6 GreenKey. If set the red signal input does not participate in the
|
||||
calculation of the chroma signal, if clear the green input is left
|
||||
out.
|
||||
7 livePortInv. If set the live data being routed to Blender Input 1
|
||||
will be inverted
|
||||
Note: The chroma output is:
|
||||
ChromaOut = [(blur - max(red,green))* (1-zeroBlue)] +
|
||||
[(255-(green*GreenKey)+(red*(1-Greenkey)))]*(1-chroma)
|
||||
|
||||
ADV index EDh (R/W): NOTOVLLEVEL
|
||||
bit 0-7 This value is used as a constant blend value when the B-level blend
|
||||
mode is selected (bit 0 of VIDCON (ADV index E4h) is 0) and the OVL
|
||||
signal is 0
|
||||
|
||||
ADV index EEh (R/W): OVLLEVEL
|
||||
bit 0-7 This value is used as a constant blend value when the B-level blend
|
||||
mode is selected (bit 0 of VIDCON (ADV index E4h) is 0) and the OVL
|
||||
signal is 1
|
||||
Reference in New Issue
Block a user