Dodajem knjige
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Matrox MGA series
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MGA-I "IS-ATLAS" Used for the Impression series. Upto 3Mb VRAM, 2Mb DRAM
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(Z-buffer) Impression Pro: Upto 4.5Mb VRAM, 4Mb DRAM (Z-buffer)
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BitBLT, 3D-acceleration
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MGA-II "IS-DUBIC","IS-TITAN" 2chips (160pin & 240pin). Used for the Ultima
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series. Upto 4MB VRAM. BitBLT. No 3D support
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? "IS-HELENA" 240 pin chip. Used for the Impression Lite/Plus series
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3D support
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? "2064W". Millenium series. 32bit VGA core. Upto 8Mb
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The Impression (original/Pro/Lite/Plus) boards have 3D functions (Gouraud
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shading), the Ultima series does not.
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The Compaq QVision 2000 card is based on the MGA-II
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VGA registers. The VGA engine can be disabled.
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3d4h index E0h (R):
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Note:
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3d4h index E1h (R/W):
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bit 0-7 ??
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3d4h index E2h (R/W):
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bit 0-7 ??
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3d4h index E3h (R/W):
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bit 0-7 ??
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3DEh index 00h (R/W):
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bit 0-7 ??
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2 If set blanks the first ~256 pixels
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4 If set the display wraps at 128Kbytes
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3DEh index 01h (R/W):
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bit 0 In 256color modes enables the bank system when set.
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1-2 ??
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3 Set for Extended 256 color modes.
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4-7 ??
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3DEh index 02h (R/W):
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bit 0-7 ??
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3DEh index 03h (R/W):
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bit 0-7 ??
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3DEh index 04h (R/W):
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bit 0-7 ??
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3DEh index 07h (R):
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3DEh index 08h (R):
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3DEh index 09h (R/W):
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bit 0-3 64K bank number.
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3DEh index 0Ah (R/W):
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bit 0-1 Display Start Address bit 16-17. Bits 0-15 are in 3d4h index 0Ch-0Dh
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Note that for 256color modes bits 0-1 of 3d4h index 0Dh appears to be
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ignored. The data intended for these bits should be written to 3d4h
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index 8 bits 5-6 instead.
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2-3 ??
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4 Appears to be set when the display start address is set ??
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6-7 ??
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3DEh index 0Ch (R/W):
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bit 0-4 ??
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7 ??
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3DEh index 0Dh (R/W):
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bit 0-7 ??
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0 If set
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1-2 Swaps lines (0/1 -> 1/0 ???)
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4 If set changes memory layout
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6 Interlaced if set ?
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7 Clock ??
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3DEh index 0Eh
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Matrox Native mode:
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In native mode the Matrox chips use a 16Kbyte memory mapped area. In the MGA-I
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(Impression) series this was apparently always at AC00h:0, in the MGA-II
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(Ultima) series it can be at AC00h:0, C800h:0, CC00h:0, D000h:0, D400h:0,
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D800h:0 or DC00h:0.
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M+0000h - M+1BFFh: Source/DMA Window
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M+1C00h - M+1CFFh: Drawing Registers
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M+1C00h D(W): Drawing Control Register (DWGCTL)
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bit 0-3 Opcode. 0: Open Line, 1: Auto/Open Autoline, 2: Closed Line,
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3: Closed Autoline, 4: Trap, 8: BitBLT, 9: Iload, Ah: Idump
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4-5 Auto line type. 0: RPL, 1: RSTR, 2: ANTI, 3: ZI
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6 Blockmode ON if set
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7 Linear BitBLT if set, XY BitBLT if clear
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16-19 ROP. 0: Black/Blackness (0), 1: NotMergePen (Not (Dst OR Src)),
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2: MaskNotPen (Dst AND Not Src), 3: NotCopyPen (Not Src),
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4: MaskPennot ((Not Dst) AND Src), 5: NOT (Not Dst), 6: XORPEN
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(Dst XOR Src), 7: NOTMASKPEN (Not (Dst AND Src)), 8: MASKPEN
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(Dst AND Src), 9: NOTXORPEN (Not Dst XOR Src), Ah: NOP (Dst),
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Bh: MERGENOTPEN (Dst OR Not Src), Ch: COPYPEN/SRCCOPY (Src),
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Dh: MERGEPENNOT ((Not Dst) OR Src), Eh: MERGEPEN (Dst OR Src),
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Fh: WHITE/WHITENESS (1)
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20-23 Trans 0-15 ??
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24 Alpha Dither. Set for RED, clear for foreground
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25-26 (BitBLT) Blt Mode. 0: Mono, 1: Planar, 2: Foreground color, 3: UCOL?
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25 (Z buffer?) ZDRWEN?. Set for Depth, clear for No Depth
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26 (Z buffer?) ZLTE?. Set for Less_Than_or_Equal, clear for Less_Than
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27 (Autoline?) Autoline foreground is Foreground Color if set, ALU data
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if clear
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(h?) Background Source is BGR/Windows if set, RGB/EC3 if clear ??
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28 (Auto line?) ABAC is Background color if set, old data if clear
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(?) HCPRS Source is 24bpp if set, 32bpp if clear
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29 Pattern enabled if set, disabled if clear
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30 Transc. Background is Transparent if set, Opaque if clear
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M+1C04h (W): Memory Access Register (MACCESS)
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bit 0-1 Pixel Width. 0: 8bpp, 1: 16bpp, 2: 32bpp
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2-3 0: Source buffer, 2: Dest buffer A, 3: Dest buffer B
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M+1C08h (W): Memory Control Wait State Register (MCTLWTST)
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Note: Set to C4001000h for IDUMPs ??
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M+1C10h (W): Destination In Register (DST0)
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M+1C14h (W): Destination In Register (DST1)
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M+1C18h (W): Z Mask Control Register (ZMSK)
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M+1C1Ch (W): Plane write Mask (PLNWT)
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bit 0-31 Each bit if set enables writing to the corresponding bit in video
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memory. FFFFFFFFh enables all of memory, FFh enables only the low
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byte of each DWORD (Blue), FF00h enables Green, FF0000h enables
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the Red byte and FF000000h enables the free byte.
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M+1C20h (W): Background Color (BCOL)
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M+1C24h (W): ForeGround Color (FCOL)
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M+1C2Ch (W): Source Register for Blit (SRCBLT)
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M+1C30h (W): Source Register 0 (SRC0)
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M+1C34h (W): Source Register 1 (SRC1)
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M+1C38h (W): Source Register 2 (SRC2)
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M+1C3Ch (W): Source Register 3 (SRC3)
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M+1C40h (W): X Y Start Address (XYSTRT)
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M+1C44h (W): X Y End Address (XYEND)
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M+1C50h (W): Funnel Shifter Control Register (SHIFT)
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bit 16-21 Rightwise Shift count (2's complement -32 to 31).
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M+1C58h (W): Sign Register (SGN)
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bit 0 (Blit) If set the X coordinate moves from right to left (decreasing
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X), if clear from left to right (increasing X).
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(Line) Set if DeltaX > DeltaY.
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1
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2 If set the Y coordinate moves from bottom to top (decreasing Y),
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if clear from top to bottom (increasing Y).
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5
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M+1C5Ch (W): Length Register (LEN)
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M+1C60h AR0
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bit 0-16 ??
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M+1C64h AR1
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M+1C68h AR2
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M+1C6Ch AR3
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M+1C70h AR4
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M+1C74h AR5
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M+1C78h AR6
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M+1C8Ch (W): Memory Pitch (PITCH)
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bit 5-12 Memory pitch in units of 32 (pixels or bytes?)
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15 If set Y is not linear ??
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M+1C90h (W): Y Address Register (YDST)
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M+1C94h (W): Memory Origin Register (YDSTORG)
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M+1C98h (W): Clipper Y Top Boundary (CYTOP)
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M+1C9Ch (W): Clipper Y Bottom Boundary (CYBOT)
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M+1CA0h (W): Clipper X Minimum Boundary (CXLEFT)
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M+1CA4h (W): Clipper X Maximum Boundary (CXRIGHT)
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M+1CA8h (W): X Address Register Left (FXLEFT)
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M+1CACh (W): X Address Register Right (FXRIGHT)
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M+1CB0h (W): X Destination Address Register (XDST)
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M+1CC0h - M+1CFFh DR0 - DR15
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M+1D00h - M+1DFFh: Start Drawing Registers
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M+1E00h - M+1EFFh: Host Registers
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M+1E00h (R/W): Source Page Register (SRCPAGE)
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M+1E04h (R/W): Destination Page Register (DSTPAGE)
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M+1E08h (R/W): Byte Accumulator Data (BYTACCDATA)
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M+1E0Ch (R/W): Address Generator Register (ADRGEN)
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M+1E10h (R/W): Bus FIFO Status Register (FIFOSTATUS)
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bit 0-6 FIFO count
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8 Full
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9 Empty
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16-22 Byte Accumulator Address
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24-29 Address Generator State
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M+1E14h D(R/W): Status Register (STATUS)
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bit 0 Bus FIFO Error Interrupt Status
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1 DMA Controller Interrupt Status
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2 Pick Interrupt Status
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3 Vsync Status
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8-11 Byte flag
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16 Drawing Engine Status. Set if the engine is busy.
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M+1E18h (W): Interrupt Clear Register (ICLEAR)
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bit 0 Write 1 to clear the Bus FIFO Interrupt
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1 Write 1 to clear the DMA Controller Interrupt
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2 Write 1 to clear the Pick Interrupt
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M+1E1Ch (R/W): interrupt Enable Register (IEN)
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bit 0 Bus FIFO Interrupt enabled if set
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1 DMA Controller Interrupt enabled if set
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2 Pick Interrupt enabled if set
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3 Vsync Interrupt enabled if set
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Note: "DMA Controller" could be "DMA Terminal Count" ?
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M+1E40h (R/W): Reset Register (RST)
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bit 0 Write 1 to perform a soft reset
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M+1E44h (R/W): Test Register (TEST)
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bit 0 VGA test
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8 Robitwren ?
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M+1E48h (R): Revision Register (REV)
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bit 0-31 A2681700h for the MGA-II (Ultima)
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A2681702h for the Impression LIte/Plus
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M+1E50h (R/W): Configuration Register (CONFIG_REG)
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M+1E54h (R/W): Operating Mode Register (OPMODE)
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bit 0 Pseudo DMA enabled if set
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1 DMA Act? enabled if set
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2-3 DMA mode. 1: Blit Write, 2: Vector Write, 3: Blit Read
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M+1E5Ch (R/W): CRTC Control (CRTC_CTRL)
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M+1E60h (R/W): VCOUNT Register (VCOUNT)
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M+1F00h - M+1FFFh: VGA registers
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Accesses to these addresses will access the VGA registers at 3xxh, I.e.
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M+1FC4h accesses 3C4h.
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M+2000h - M+3BFFh: Destination Window
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M+3C00h - M+3C7Fh: RamDAC Registers
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The RamDAC registers are mapped 4 addresses apart (I.e. REG00 at M+3C00h,
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REG01 at M+3C04h...).
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M+3C80h - M+3CFFh: Dubic Chip Registers
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M+3C80h (R/W): DUB_SEL
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M+3C84h (R/W): NDX_PTR
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The indexed DUBIC registers are accessed by writing the index to M+3C84h
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and reading or writing the data at M+3C88h.
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M+3C88h (R/W): DUB_DATA
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Data port for the indexed registers
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M+3C84h index 00h (R/W): DUB_CTL
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M+3C84h index 01h (R/W): KEY_COL
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M+3C84h index 02h (R/W): KEY_MSK
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M+3C84h index 03h W(R/W): DBX_MIN_MAX
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M+3C84h index 05h W(R/W): DBY_MIN_MAX
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M+3C84h index 07h (R/W): OVS_COL
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M+3C84h index 08h (R/W): CUR_X
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M+3C84h index 09h (R/W): CUR_Y
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M+3C84h index 0Ah (R/W): DUB_CTL2
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M+3C84h index 0Ch (R/W): DUB_COL0
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M+3C84h index 0Dh (R/W): DUB_COL1
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M+3C84h index 0Eh (R/W): CRC_CTL
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M+3C84h index 0Fh (R/W): CRC_DAT
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M+3C83h (R/W): LASER
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M+3C84h (R/W): MOUSE0
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M+3C85h (R/W): MOUSE1
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M+3C86h (R/W): MOUSE2
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M+3C87h (R/W): MOUSE3
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M+3D00h - M+3D7Fh: Viwic Chip Registers
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M+3D80h - M+3DFFh: Clock Generator
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M+3E00h - M+3FFFh: Expansion Devices
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Identifying Matrox chips:
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Modes (VGA part):
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27h G 800 600 PL4
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2Ah G 1024 768 PL4
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33h G 640 400 P8
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34h G 640 480 P8
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39h G 800 600 P8
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3Bh G 1024 768 P8
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41h T 90 25
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43h T 120 25
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44h T 132 25
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----------10BD-----------------------------------
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INT 10 - VIDEO - Matrox - Check for Matrox card
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AX = BDFFh
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Returns: AX = 00BDh if Matrox card installed
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DX = BIOS segment
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----------10BD-----------------------------------
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INT 10 - VIDEO - Matrox
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AX = BDFEh
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AL = Emulation
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43h CGA emulation
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45h EGA emulation
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4Dh Hercules emulation
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56h VGA emulation
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ES:DI -> signature string "Calamity"
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Switches to the desired emulation
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MCA specifics:
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POS ID - 80ECh (Ultima)
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POS registers:
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00h bit 0 Set if adapter enabled
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01h bit 0-2 Memory Mapping. Controls location of the 16K aperture
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0: AC00h, 2: C800h, 3: CC00h, 4: D000h, 5: D400h, 6: D800h,
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7: DC00h
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